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Figure 7: Configuration Register Write and Read Operations
Parameter
Description
f
SCLK frequency
SCLK
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
SCLK frequency, single access
No delay between address and data byte
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
t
CSn low to positive edge on SCLK, in power-down mode
sp,pd
t
CSn low to positive edge on SCLK, in active mode
sp
t
Clock high
ch
t
Clock low
cl
t
Clock rise time
rise
t
Clock fall time
fall
t
Setup data (negative SCLK edge) to
sd
positive edge on SCLK
(t
applies between address and data bytes, and
sd
between data bytes)
t
Hold data after positive edge on SCLK
hd
t
Negative edge on
ns
Note: The minimum t
sp,pd
CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down
depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator
start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK.
10.1
Chip Status Byte
When the header byte, data byte or, command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC2500 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYn signal; this signal must go low
SCLK
to CSn high
Table 16: SPI Interface Timing Requirements
figure in Table 16 can be used in cases where the user does not read the
SWRS040C
Min
-
150
20
50
50
-
-
Single access
55
Burst access
76
20
20
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel
CC2500
Max
Units
10
MHz
9
MHz
6.5
MHz
µs
-
ns
-
ns
-
ns
5
ns
5
ns
-
ns
-
ns
-
ns
-
ns
Page 22 of 89
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