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configuration should only be updated when the
chip is in this state. The RX state will be active
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
The last four bits (3:0) in the status byte
contains FIFO_BYTES_AVAILABLE. For read
operations (the R/W bit in the header byte is
set to 1), the FIFO_BYTES_AVAILABLE field
contains the number of bytes available for
Bits
Name
7
CHIP_RDYn
6:4
STATE[2:0]
3:0
FIFO_BYTES_AVAILABLE[3:0]
10.2
Register Access
The configuration registers of the CC2500 are
located on SPI addresses from 0x00 to 0x2E.
Table 35 on page 58 lists all configuration
registers. It is highly recommended to use
®
SmartRF
Studio [5] to generate optimum
register settings. The detailed description of
each register is found in Section 32.1, starting
on page 61. All configuration registers can be
both written to and read. The R/W bit controls
if the register should be written to or read.
When writing to registers, the status byte is
sent on the SO pin each time a header byte or
data byte is transmitted on the SI pin. When
reading from registers, the status byte is sent
on the SO pin each time a header byte is
transmitted on the SI pin.
Registers with consecutive addresses can be
accessed in an efficient way by setting the
reading
operations (the R/W bit in the header byte is
set to 0), the FIFO_BYTES_AVAILABLE field
contains the number of bytes that can be
written
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 17 gives a status byte summary.
Description
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
Indicates the current main state machine mode
Value
State
000
IDLE
001
RX
010
TX
011
FSTXON
100
CALIBRATE
101
SETTLING
110
RXFIFO_OVERFLOW
111
TXFIFO_UNDERFLOW
The number of bytes available in the RX FIFO or free bytes in the TX FIFO
Table 17: Status Byte Summary
burst bit (B) in the header byte. The address
bits
internal address counter. This counter is
incremented by one each new byte (every 8
clock pulses). The burst access is either a
read or a write access and must be terminated
by setting CSn high.
For register addresses in the range 0x30-
0x3D, the burst bit is used to select between
status registers, burst bit is one, and command
strobes, burst bit is zero (see Section 10.4
below). Because of this, burst access is not
available for status registers and they must be
accessed one at a time. The status registers
can only be read.
10.3
When reading register fields over the SPI
interface while the register fields are updated
SWRS040C
from
the
RX
FIFO.
to
the
TX
Description
Idle state
(Also reported for some transitional states
instead of SETTLING or CALIBRATE)
Receive mode
Transmit mode
Frequency synthesizer is on, ready to start
transmitting
Frequency synthesizer calibration is running
PLL is settling
RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX
TX FIFO has underflowed. Acknowledge with
SFTX
(A
– A
) set the start address in an
5
0
SPI Read
CC2500
For
write
FIFO.
When
Page 23 of 89
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