Chip Status Byte; Register Access - Texas Instruments CC1101 Manual

10.1 Chip Status Byte

When the header byte, data byte, or command
strobe is sent on the SPI interface, the chip
status byte is sent by the
The status byte contains key status signals,
useful for the MCU. The first bit, s7, is the
CHIP_RDYn signal and this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core are on in
the IDLE state, but all other modules are in
power down. The frequency and channel
configuration should only be updated when the
chip is in this state. The RX state will be active
Bits Name
7 CHIP_RDYn
6:4 STATE[2:0]
3:0 FIFO_BYTES_AVAILABLE[3:0]

10.2 Register Access

The configuration registers on the
located on SPI addresses from 0x00 to 0x2E.
Table 43 on page 68 lists all configuration
registers. It is highly recommended to use
SmartRF Studio [5] to generate optimum
register settings. The detailed description of
each register is found in Section 29.1 and
29.2, starting on page 71. All configuration
registers can be both written to and read. The
R/W ¯ bit controls if the register should be
written to or read. When writing to registers,
CC1101
on the SO pin.
Description
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
Indicates the current main state machine mode
Value State
000 IDLE
001 RX
010 TX
011 FSTXON
100 CALIBRATE
101 SETTLING
110 RXFIFO_OVERFLOW
111 TXFIFO_UNDERFLOW
The number of bytes available in the RX FIFO or free bytes in the TX FIFO
Table 23: Status Byte Summary
CC1101
are
SWRS061H
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
The last four bits (3:0) in the status byte
contains FIFO_BYTES_AVAILABLE. For read
operations (the R/W ¯ bit in the header byte is
set to 1), the FIFO_BYTES_AVAILABLE field
contains the number of bytes available for
reading from the
operations (the R/W ¯ bit in the header byte is
set to 0), the FIFO_BYTES_AVAILABLE field
contains the number of bytes that can be
written to the
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 23 gives a status byte summary.
Description
IDLE state
(Also reported for some transitional states instead
of SETTLING or CALIBRATE)
Receive mode
Transmit mode
Fast TX ready
Frequency synthesizer calibration is running
PLL is settling
RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX
TX FIFO has underflowed. Acknowledge with
SFTX
the status byte is sent on the SO pin each time
a header byte or data byte is transmitted on
the SI pin. When reading from registers, the
status byte is sent on the SO pin each time a
header byte is transmitted on the SI pin.
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit (B) in the header byte. The address
– A
bits (A ) set the start address in an
5 0
internal address counter. This counter is
incremented by one each new byte (every 8
CC1101
RX FIFO. For write
TX FIFO. When
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