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Renesas SH7750R 32-bit Microcontroller Manuals
Manuals and User Guides for Renesas SH7750R 32-bit Microcontroller. We have
1
Renesas SH7750R 32-bit Microcontroller manual available for free PDF download: Hardware Manual
Renesas SH7750R Hardware Manual (1162 pages)
Brand:
Renesas
| Category:
Computer Hardware
| Size: 6.68 MB
Table of Contents
Table of Contents
47
Section 1 Overview
85
SH7750, SH7750S, SH7750R Groups Features
85
Table 1.1 LSI Features
85
Block Diagram
93
Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions
93
Pin Arrangement
94
Figure 1.2 Pin Arrangement (256-Pin BGA)
94
Section 1 Overview
94
Figure 1.3 Pin Arrangement (208-Pin QFP)
95
Figure 1.4 Pin Arrangement (264-Pin CSP)
96
Figure 1.5 Pin Arrangement (292-Pin BGA)
97
Pin Functions
98
Pin Functions (256-Pin BGA)
98
Table 1.2 Pin Functions
98
Pin Functions (208-Pin QFP)
108
Table 1.3 Pin Functions
108
Pin Functions (264-Pin CSP)
116
Table 1.4 Pin Functions
116
Pin Functions (292-Pin BGA)
126
Table 1.5 Pin Functions
126
Section 2 Programming Model
137
Data Formats
137
Figure 2.1 Data Formats
137
Register Configuration
138
Privileged Mode and Banks
138
Table 2.1 Initial Register Values
139
Figure 2.2 CPU Register Configuration in each Processor Mode
140
General Registers
141
Figure 2.3 General Registers
142
Floating-Point Registers
143
Figure 2.4 Floating-Point Registers
145
Control Registers
146
System Registers
147
Memory-Mapped Registers
149
Data Format in Registers
150
Data Formats in Memory
150
Processor States
151
Figure 2.5 Data Formats in Memory
151
Figure 2.6 Processor State Transitions
152
Processor Modes
153
Section 3 Memory Management Unit (MMU)
155
Overview
155
Features
155
Role of the MMU
155
Figure 3.1 Role of the MMU
157
Register Configuration
158
Caution
158
Table 3.1 MMU Registers
158
Register Descriptions
159
Figure 3.2 MMU-Related Registers
159
Address Space
163
Physical Address Space
163
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
163
Figure 3.4 P4 Area
165
External Memory Space
166
Figure 3.5 External Memory Space
166
Virtual Address Space
167
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
167
On-Chip RAM Space
168
Address Translation
169
Single Virtual Memory Mode and Multiple Virtual Memory Mode
169
Address Space Identifier (ASID)
169
TLB Functions
170
Unified TLB (UTLB) Configuration
170
Figure 3.7 UTLB Configuration
170
Figure 3.8 Relationship between Page Size and Address Format
171
Instruction TLB (ITLB) Configuration
174
Address Translation Method
174
Figure 3.9 ITLB Configuration
174
Figure 3.10 Flowchart of Memory Access Using UTLB
175
Figure 3.11 Flowchart of Memory Access Using ITLB
176
MMU Functions
177
MMU Hardware Management
177
MMU Software Management
177
MMU Instruction (LDTLB)
177
Hardware ITLB Miss Handling
178
Figure 3.12 Operation of LDTLB Instruction
178
Avoiding Synonym Problems
179
MMU Exceptions
180
Instruction TLB Multiple Hit Exception
180
Instruction TLB Miss Exception
180
Instruction TLB Protection Violation Exception
182
Data TLB Multiple Hit Exception
182
Data TLB Miss Exception
183
Data TLB Protection Violation Exception
184
Initial Page Write Exception
185
Memory-Mapped TLB Configuration
186
ITLB Address Array
187
Figure 3.13 Memory-Mapped ITLB Address Array
187
ITLB Data Array 1
188
Figure 3.14 Memory-Mapped ITLB Data Array 1
188
ITLB Data Array 2
189
Figure 3.15 Memory-Mapped ITLB Data Array 2
189
UTLB Address Array
190
UTLB Data Array 1
191
Figure 3.16 Memory-Mapped UTLB Address Array
191
UTLB Data Array 2
192
Figure 3.17 Memory-Mapped UTLB Data Array 1
192
Usage Notes
193
Figure 3.18 Memory-Mapped UTLB Data Array 2
193
Section 4 Caches
195
Overview
195
Features
195
Table 4.1 Cache Features (SH7750, SH7750S)
195
Table 4.2 Cache Features (SH7750R)
196
Table 4.3 Features of Store Queues
196
Register Configuration
197
Table 4.4 Cache Control Registers
197
Register Descriptions
198
Figure 4.1 Cache and Store Queue Control Registers
198
Operand Cache (OC)
200
Configuration
200
Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S)
201
Figure 4.3 Configuration of Operand Cache (SH7750R)
202
Read Operation
204
Write Operation
205
Write-Back Buffer
206
Write-Through Buffer
206
Figure 4.4 Configuration of Write-Back Buffer
206
Figure 4.5 Configuration of Write-Through Buffer
206
RAM Mode
207
OC Index Mode
208
Coherency between Cache and External Memory
209
Prefetch Operation
209
Notes on Using Cache Enhanced Mode (SH7750R Only)
209
Instruction Cache (IC)
212
Configuration
212
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
212
Figure 4.7 Configuration of Instruction Cache (SH7750R)
213
Read Operation
214
IC Index Mode
215
Memory-Mapped Cache Configuration (SH7750, SH7750S)
215
IC Address Array
215
IC Data Array
216
Figure 4.8 Memory-Mapped IC Address Array
216
OC Address Array
217
Figure 4.9 Memory-Mapped IC Data Array
217
OC Data Array
219
Figure 4.10 Memory-Mapped OC Address Array
219
Memory-Mapped Cache Configuration (SH7750R)
220
Figure 4.11 Memory-Mapped OC Data Array
220
IC Address Array
221
IC Data Array
222
Figure 4.12 Memory-Mapped IC Address Array
222
OC Address Array
223
Figure 4.13 Memory-Mapped IC Data Array
223
Figure 4.14 Memory-Mapped OC Address Array
224
OC Data Array
225
Figure 4.15 Memory-Mapped OC Data Array
225
Summary of the Memory-Mapping of the OC
226
Store Queues
226
SQ Configuration
226
SQ Writes
227
Transfer to External Memory
227
Figure 4.16 Store Queue Configuration
227
SQ Protection
229
Reading the Sqs (SH7750R Only)
229
SQ Usage Notes
230
Section 5 Exceptions
233
Overview
233
Features
233
Register Configuration
233
Table 5.1 Exception-Related Registers
233
Register Descriptions
234
Figure 5.1 Register Bit Configurations
234
Exception Handling Functions
235
Exception Handling Flow
235
Exception Handling Vector Addresses
235
Exception Types and Priorities
236
Table 5.2 Exceptions
236
Exception Flow
239
Figure 5.2 Instruction Execution and Exception Handling
239
Exception Source Acceptance
240
Figure 5.3 Example of General Exception Acceptance Order
241
Exception Requests and BL Bit
242
Return from Exception Handling
242
Description of Exceptions
242
Resets
243
Table 5.3 Types of Reset
245
General Exceptions
248
Interrupts
262
Priority Order with Multiple Exceptions
265
Usage Notes
266
Restrictions
267
Section 6 Floating-Point Unit (FPU)
269
Overview
269
Data Formats
269
Floating-Point Format
269
Figure 6.1 Format of Single-Precision Floating-Point Number
269
Figure 6.2 Format of Double-Precision Floating-Point Number
270
Table 6.1 Floating-Point Number Formats and Parameters
270
Non-Numbers (Nan)
271
Table 6.2 Floating-Point Ranges
271
Denormalized Numbers
272
Figure 6.3 Single-Precision Nan Bit Pattern
272
Registers
273
Floating-Point Registers
273
Figure 6.4 Floating-Point Registers
274
Floating-Point Status/Control Register (FPSCR)
275
Floating-Point Communication Register (FPUL)
276
Rounding
277
Floating-Point Exceptions
277
Graphics Support Functions
279
Geometric Operation Instructions
279
Pair Single-Precision Data Transfer
280
Usage Notes
281
Rounding Mode and Underflow Flag
281
Setting of Overflow Flag by FIPR or FTRV Instruction
282
Sign of Operation Result When Using FIPR or FTRV Instruction
283
Notes on Double-Precision FADD and FSUB Instructions
283
Notes on FPU Double-Precision Operation Instructions (SH7750 Only)
284
Table 6.3 Incorrect Operation Result
287
Table 6.4 FDIV Drm, Drn (Drn/Drm → Drn)
288
Table 6.5 FADD Drm, Drn (Drn + Drm → Drn) FSUB Drm, Drn (Drn − Drm → Drn)
289
Table 6.6 FMUL Drm, Drn (Drn*Drm → Drn)
289
Table 6.7 TRAP Routine Processing
291
Section 7 Instruction Set
293
Execution Environment
293
Addressing Modes
295
Instruction Set
299
Table 7.2 Notation Used in Instruction List
299
Table 7.3 Fixed-Point Transfer Instructions
300
Table 7.4 Arithmetic Operation Instructions
302
Table 7.5 Logic Operation Instructions
304
Table 7.6 Shift Instructions
305
Table 7.7 Branch Instructions
306
Table 7.8 System Control Instructions
307
Table 7.9 Floating-Point Single-Precision Instructions
309
Table 7.10 Floating-Point Double-Precision Instructions
310
Table 7.11 Floating-Point Control Instructions
310
Usage Notes
311
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD)
311
Table 7.12 Floating-Point Graphics Acceleration Instructions
311
Section 8 Pipelining
315
Pipelines
315
Figure 8.1 Basic Pipelines
316
Figure 8.2 Instruction Execution Patterns
317
Parallel-Executability
322
Table 8.1 Instruction Groups
322
Execution Cycles and Pipeline Stalling
326
Table 8.2 Parallel-Executability
326
Figure 8.3 Examples of Pipelined Execution
329
Table 8.3 Execution Cycles
333
Usage Notes
342
Section 9 Power-Down Modes
343
Overview
343
Types of Power-Down Modes
343
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
344
Register Configuration
345
Pin Configuration
345
Table 9.2 Power-Down Mode Registers
345
Table 9.3 Power-Down Mode Pins
345
Register Descriptions
346
Standby Control Register (STBCR)
346
Peripheral Module Pin High Impedance Control
348
Peripheral Module Pin Pull-Up Control
349
Standby Control Register 2 (STBCR2)
349
Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
351
Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
352
Sleep Mode
352
Transition to Sleep Mode
352
Exit from Sleep Mode
353
Deep Sleep Mode
353
Transition to Deep Sleep Mode
353
Exit from Deep Sleep Mode
353
Standby Mode
354
Transition to Standby Mode
354
Table 9.4 State of Registers in Standby Mode
354
Exit from Standby Mode
355
Clock Pause Function
355
Module Standby Function
356
Transition to Module Standby Function
356
Exit from Module Standby Function
357
Hardware Standby Mode (SH7750S, SH7750R Only)
358
Transition to Hardware Standby Mode
358
Exit from Hardware Standby Mode
358
Usage Notes
359
STATUS Pin Change Timing
359
In Reset
360
Figure 9.1 STATUS Output in Power-On Reset
360
Figure 9.2 STATUS Output in Manual Reset
360
In Exit from Standby Mode
361
Figure 9.3 STATUS Output in Standby → Interrupt Sequence
361
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence
361
Figure 9.5 STATUS Output in Standby → Manual Reset Sequence
362
In Exit from Sleep Mode
363
Figure 9.6 STATUS Output in Sleep → Interrupt Sequence
363
Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence
363
Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence
364
In Exit from Deep Sleep Mode
365
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
365
Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
365
Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence
366
Hardware Standby Mode Timing (SH7750S, SH7750R Only)
367
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
367
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
368
Figure 9.14 Timing When Power Other than VDD-RTC Is off
369
Figure 9.15 Timing When VDD-RTC Power Is off → on
369
Usage Notes
370
Note on Current Consumption
370
Section 10 Clock Oscillation Circuits
371
Overview
371
Features
371
Overview of CPG
373
Block Diagram of CPG
373
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S)
373
Figure 10.1 (2) Block Diagram of CPG (SH7750R)
374
CPG Pin Configuration
376
CPG Register Configuration
376
Table 10.1 CPG Pins
376
Table 10.2 CPG Register
376
Clock Operating Modes
377
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S)
377
Table 10.3 (2) Clock Operating Modes (SH7750R)
377
Table 10.4 FRQCR Settings and Internal Clock Frequencies
378
CPG Register Description
379
Frequency Control Register (FRQCR)
379
Changing the Frequency
382
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
382
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
382
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
383
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
383
Changing CPU or Peripheral Module Clock Division Ratio
383
Output Clock Control
383
Overview of Watchdog Timer
384
Block Diagram
384
Figure 10.2 Block Diagram of WDT
384
Register Configuration
385
WDT Register Descriptions
385
Watchdog Timer Counter (WTCNT)
385
Table 10.5 WDT Registers
385
Watchdog Timer Control/Status Register (WTCSR)
386
Notes on Register Access
389
Using the WDT
389
Standby Clearing Procedure
389
Figure 10.3 Writing to WTCNT and WTCSR
389
Frequency Changing Procedure
390
Using Watchdog Timer Mode
390
Using Interval Timer Mode
391
Notes on Board Design
391
Figure 10.4 Points for Attention When Using Crystal Resonator
391
Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
392
Usage Notes
393
Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S)
393
Section 11 Realtime Clock (RTC)
395
Overview
395
Features
395
Block Diagram
396
Figure 11.1 Block Diagram of RTC
396
Pin Configuration
397
Register Configuration
397
Table 11.1 RTC Pins
397
Table 11.2 RTC Registers
397
Register Descriptions
399
64 Hz Counter (R64CNT)
399
Second Counter (RSECCNT)
400
Minute Counter (RMINCNT)
400
Hour Counter (RHRCNT)
401
Day-Of-Week Counter (RWKCNT)
401
Day Counter (RDAYCNT)
402
Month Counter (RMONCNT)
402
Year Counter (RYRCNT)
403
Second Alarm Register (RSECAR)
404
Minute Alarm Register (RMINAR)
404
Hour Alarm Register (RHRAR)
405
Day-Of-Week Alarm Register (RWKAR)
405
Day Alarm Register (RDAYAR)
406
Month Alarm Register (RMONAR)
407
RTC Control Register 1 (RCR1)
407
RTC Control Register 2 (RCR2)
409
RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR)
411
(SH7750R Only)
411
Operation
413
Time Setting Procedures
413
Figure 11.2 Examples of Time Setting Procedures
413
Time Reading Procedures
414
Figure 11.3 Examples of Time Reading Procedures
415
Alarm Function
416
Figure 11.4 Example of Use of Alarm Function
416
Interrupts
417
Usage Notes
417
Register Initialization
417
Carry Flag and Interrupt Flag in Standby Mode
417
Crystal Oscillator Circuit
417
Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values)
417
RTC Register Settings (SH7750 Only)
418
Figure 11.5 Example of Crystal Oscillator Circuit Connection
418
Section 12 Timer Unit (TMU)
421
Overview
421
Features
421
Block Diagram
422
Pin Configuration
422
Figure 12.1 Block Diagram of TMU
422
Table 12.1 TMU Pins
422
Register Configuration
423
Table 12.2 TMU Registers
423
Register Descriptions
425
Timer Output Control Register (TOCR)
425
Timer Start Register (TSTR)
426
Timer Start Register 2 (TSTR2) (SH7750R Only)
427
Timer Constant Registers (TCOR)
428
Timer Counters (TCNT)
428
Timer Control Registers (TCR)
429
Input Capture Register 2 (TCPR2)
434
Operation
434
Counter Operation
434
Figure 12.2 Example of Count Operation Setting Procedure
435
Figure 12.3 TCNT Auto-Reload Operation
436
Figure 12.4 Count Timing When Operating on Internal Clock
436
Input Capture Function
437
Figure 12.5 Count Timing When Operating on External Clock
437
Figure 12.6 Count Timing When Operating on On-Chip RTC Output Clock
437
Figure 12.7 Operation Timing When Using Input Capture Function
438
Interrupts
439
Usage Notes
439
Register Writes
439
Table 12.3 TMU Interrupt Sources
439
Underflow Flag Writes (SH7750 Only)
440
TCNT Register Reads
440
Resetting the RTC Frequency Divider
440
External Clock Frequency
440
Section 13 Bus State Controller (BSC)
441
Overview
441
Features
441
Block Diagram
443
Figure 13.1 Block Diagram of BSC
443
Pin Configuration
444
Table 13.1 BSC Pins
444
Register Configuration
448
Table 13.2 BSC Registers
448
Overview of Areas
449
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
449
Table 13.3 External Memory Space Map
450
Figure 13.3 External Memory Space Allocation
451
PCMCIA Support
452
Table 13.4 PCMCIA Interface Features
452
Table 13.5 PCMCIA Support Interfaces
453
Register Descriptions
456
Bus Control Register 1 (BCR1)
456
Bus Control Register 2 (BCR2)
465
Bus Control Register 3 (BCR3) (SH7750R Only)
467
Bus Control Register 4 (BCR4) (SH7750R Only)
468
Figure 13.4 Example of RDY Sampling Timing at Which BCR4 Is Set
469
Wait Control Register 1 (WCR1)
472
Wait Control Register 2 (WCR2)
475
Table 13.6 MPX Interface Is Selected (Areas 0 to 6)
482
Wait Control Register 3 (WCR3)
483
Memory Control Register (MCR)
485
PCMCIA Control Register (PCR)
493
Synchronous DRAM Mode Register (SDMR)
497
Refresh Timer Control/Status Register (RTCSR)
499
Refresh Timer Counter (RTCNT)
502
Refresh Time Constant Register (RTCOR)
503
Refresh Count Register (RFCR)
504
13.2.15 Notes on Accessing Refresh Control Registers
504
Operation
505
Endian/Access Size and Data Alignment
505
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
505
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment
507
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment
508
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
509
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
510
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
511
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment
512
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment
513
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment
514
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment
515
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment
516
Areas
517
SRAM Interface
522
Figure 13.6 Basic Timing of SRAM Interface
523
Figure 13.7 Example of 64-Bit Data Width SRAM Connection
524
Figure 13.8 Example of 32-Bit Data Width SRAM Connection
525
Figure 13.9 Example of 16-Bit Data Width SRAM Connection
526
Figure 13.10 Example of 8-Bit Data Width SRAM Connection
527
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)
528
Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)
529
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (Ans = 1, Anw = 4, Anh = 2)
530
DRAM Interface
531
Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)
532
Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3)
533
Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3)
534
Table 13.15 Relationship between AMXEXT and AMX2-0 Bits and Address Multiplexing
535
Figure 13.17 Basic DRAM Access Timing
536
Figure 13.18 DRAM Wait State Timing
537
Figure 13.19 DRAM Burst Access Timing
538
Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, Anw = 0, TPC = 1)
539
Figure 13.21 Burst Access Timing in DRAM EDO Mode
540
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)
541
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)
542
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS down Mode Start (EDO Mode, RCD = 0, Anw = 0)
543
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS down Mode Continuation (EDO Mode, RCD = 0, Anw = 0)
544
Figure 13.23 CAS-Before-RAS Refresh Operation
545
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (tras = 0, TRC = 1)
546
Figure 13.25 DRAM Self-Refresh Cycle Timing
548
Synchronous DRAM Interface
549
Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)
550
Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
551
Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2-AMX0 = 011, AMXEXT = 0)
552
Figure 13.28 Basic Timing for Synchronous DRAM Burst Read
553
Figure 13.29 Basic Timing for Synchronous DRAM Single Read
555
Figure 13.30 Basic Timing for Synchronous DRAM Burst Write
557
Figure 13.31 Basic Timing for Synchronous DRAM Single Write
558
Figure 13.32 Burst Read Timing
560
Figure 13.33 Burst Read Timing (RAS Down, same Row Address)
561
Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)
562
Figure 13.35 Burst Write Timing
563
Figure 13.36 Burst Write Timing (same Row Address)
564
Figure 13.37 Burst Write Timing (Different Row Addresses)
565
Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding
567
Table 13.17 Cycles for Which Pipeline Access Is Possible
568
Figure 13.39 Auto-Refresh Operation
569
Figure 13.40 Synchronous DRAM Auto-Refresh Timing
570
Figure 13.41 Synchronous DRAM Self-Refresh Timing
571
Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL)
574
Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)
575
Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)
576
Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM
578
Figure 13.45 Example of the Connection of Synchronous DRAM with 64-Bit Bus Width
579
Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width (TRAS[2:0] = 001, TRC[2:0] = 001)
580
Burst ROM Interface
581
Figure 13.47 Burst ROM Basic Access Timing
582
Figure 13.48 Burst ROM Wait Access Timing
583
PCMCIA Interface
584
Figure 13.49 Burst ROM Wait Access Timing
584
Table 13.18 Relationship between Address and CE When Using PCMCIA Interface
586
Figure 13.50 Example of PCMCIA Interface
588
Figure 13.51 Basic Timing for PCMCIA Memory Card Interface
589
Figure 13.52 Wait Timing for PCMCIA Memory Card Interface
590
Figure 13.53 PCMCIA Space Allocation
591
Figure 13.54 Basic Timing for PCMCIA I/O Card Interface
592
Figure 13.55 Wait Timing for PCMCIA I/O Card Interface
593
Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
594
MPX Interface
595
Figure 13.57 Example of 64-Bit Data Width MPX Connection
596
Figure 13.58 MPX Interface Timing 1
597
Figure 13.59 MPX Interface Timing 2
598
Figure 13.60 MPX Interface Timing 3
599
Figure 13.61 MPX Interface Timing 4
600
Figure 13.62 MPX Interface Timing 5
601
Figure 13.63 MPX Interface Timing 6
602
Figure 13.64 MPX Interface Timing 7
603
Figure 13.65 MPX Interface Timing 8
604
Figure 13.66 MPX Interface Timing 9
605
Figure 13.67 MPX Interface Timing 10
606
Figure 13.68 MPX Interface Timing 11
607
Figure 13.69 MPX Interface Timing 12
608
Figure 13.70 MPX Interface Timing
609
Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, Anw = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
610
Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, Anw = 0, no External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
611
Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, Anw = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
612
Byte Control SRAM Interface
613
Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM
614
Figure 13.75 Byte Control SRAM Basic Read Cycle (no Wait)
615
Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
616
Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait)
617
13.3.10 Waits between Access Cycles
618
Figure 13.78 Waits between Access Cycles
619
13.3.11 Bus Arbitration
620
Figure 13.79 Arbitration Sequence
622
13.3.12 Master Mode
623
13.3.13 Slave Mode
624
13.3.14 Partial-Sharing Master Mode
625
13.3.15 Cooperation between Master and Slave
626
13.3.16 Notes on Usage
627
Section 14 Direct Memory Access Controller (DMAC)
629
Overview
629
Features
629
Block Diagram (SH7750, SH7750S)
631
Figure 14.1 Block Diagram of DMAC
632
Pin Configuration (SH7750, SH7750S)
633
Table 14.1 DMAC Pins
633
Register Configuration (SH7750, SH7750S)
634
Table 14.2 DMAC Pins in DDT Mode
634
Table 14.3 DMAC Registers
634
Register Descriptions (SH7750, SH7750S)
636
DMA Source Address Registers 0-3 (SAR0-SAR3)
636
DMA Destination Address Registers 0-3 (DAR0-DAR3)
637
DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)
638
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
639
DMA Operation Register (DMAOR)
648
Operation
651
DMA Transfer Procedure
651
Figure 14.2 DMAC Transfer Flowchart
652
DMA Transfer Requests
653
Table 14.4 Selecting External Request Mode with RS Bits
654
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
656
Channel Priorities
657
Figure 14.3 Round Robin Mode
658
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
659
Types of DMA Transfer
660
Table 14.6 Supported DMA Transfers
660
Figure 14.5 Data Flow in Single Address Mode
661
Figure 14.6 DMA Transfer Timing in Single Address Mode
662
Figure 14.7 Operation in Dual Address Mode
663
Figure 14.8 Example of Transfer Timing in Dual Address Mode
664
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
665
Figure 14.10 Example of DMA Transfer in Burst Mode
665
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode
666
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode
667
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
668
Number of Bus Cycle States and DREQ Pin Sampling Timing
669
Figure 14.11 Bus Handling with Two DMAC Channels Operating
669
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
672
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
673
Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
682
Ending DMA Transfer
683
Examples of Use
686
Examples of Transfer between External Memory and an External Device with
686
Dack
686
Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings
686
On-Demand Data Transfer Mode (DDT Mode)
687
Operation
687
Figure 14.23 On-Demand Transfer Mode Block Diagram
687
Pins in DDT Mode
689
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
689
Figure 14.25 Data Transfer Request Format
690
Transfer Request Acceptance on each Channel
692
Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer
693
Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer
694
Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer
695
Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
696
Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
697
Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
698
Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
699
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
700
Figure 14.34 Handshake Protocol Without Use of Data Bus (Channel 0 On-Demand Data Transfer)
701
Figure 14.35 Read from Synchronous DRAM Precharge Bank
702
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)
702
Figure 14.37 Read from Synchronous DRAM (Row Hit)
703
Figure 14.38 Write to Synchronous DRAM Precharge Bank
703
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)
704
Figure 14.40 Write to Synchronous DRAM (Row Hit)
704
Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
705
Figure 14.42 DDT Mode Setting
706
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/External Device → External Bus Data Transfer
706
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/External Bus → External Device Data Transfer
707
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer
708
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer
709
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/Dma Transfer Request to Channels 1-3 Using Data Bus
710
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Without Using Data Bus
711
Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data
712
Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
713
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
714
Notes on Use of DDT Module
715
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
715
Configuration of the DMAC (SH7750R)
718
Block Diagram of the DMAC
718
Figure 14.53 Block Diagram of the DMAC
719
Pin Configuration (SH7750R)
720
Table 14.11 DMAC Pins
720
Register Configuration (SH7750R)
721
Table 14.12 DMAC Pins in DDT Mode
721
Table 14.13 Register Configuration
722
Register Descriptions (SH7750R)
724
DMA Source Address Registers 0-7 (SAR0-SAR7)
724
DMA Destination Address Registers 0-7 (DAR0-DAR7)
724
DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7)
725
DMA Channel Control Registers 0-7 (CHCR0-CHCR7)
725
DMA Operation Register (DMAOR)
729
Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)
730
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)
730
Operation (SH7750R)
731
Channel Specification for a Normal DMA Transfer
731
Channel Specification for DDT-Mode DMA Transfer
731
Transfer Channel Notification in DDT Mode
732
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode
732
Table 14.16 Function of BAVL
732
Clearing Request Queues by DTR Format
733
Interrupt-Request Codes
733
Table 14.17 DTR Format for Clearing Request Queues
733
Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
734
Table 14.18 DMAC Interrupt-Request Codes
734
Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte
735
Usage Notes
736
Section 15 Serial Communication Interface (SCI)
739
Overview
739
Features
739
Block Diagram
741
Figure 15.1 Block Diagram of SCI
741
Pin Configuration
742
Register Configuration
742
Table 15.1 SCI Pins
742
Register Descriptions
743
Receive Shift Register (SCRSR1)
743
Table 15.2 SCI Registers
743
Receive Data Register (SCRDR1)
744
Transmit Shift Register (SCTSR1)
744
Transmit Data Register (SCTDR1)
745
Serial Mode Register (SCSMR1)
745
Serial Control Register (SCSCR1)
748
Serial Status Register (SCSSR1)
751
Serial Port Register (SCSPTR1)
755
Figure 15.2 MD0/SCK Pin
758
Figure 15.3 Md7/Txd Pin
759
Figure 15.4 Rxd Pin
759
Bit Rate Register (SCBRR1)
760
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
761
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
765
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator
766
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
767
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
767
Operation
768
Overview
768
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
769
Operation in Asynchronous Mode
770
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
770
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
771
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
772
Figure 15.6 Relation between Output Clock and Transfer Data Phase
773
Figure 15.7 Sample SCI Initialization Flowchart
774
Figure 15.8 Sample Serial Transmission Flowchart
775
Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
777
Figure 15.10 Sample Serial Reception Flowchart (1)
778
Figure 15.10 Sample Serial Reception Flowchart (2)
779
Table 15.11 Receive Error Conditions
780
Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
781
Multiprocessor Communication Function
782
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
783
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
784
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
786
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)
788
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)
789
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
790
Operation in Synchronous Mode
791
Figure 15.17 Data Format in Synchronous Communication
791
Figure 15.18 Sample SCI Initialization Flowchart
793
Figure 15.19 Sample Serial Transmission Flowchart
794
Figure 15.20 Example of SCI Transmit Operation
796
Figure 15.21 Sample Serial Reception Flowchart (1)
797
Figure 15.21 Sample Serial Reception Flowchart (2)
798
Figure 15.22 Example of SCI Receive Operation
799
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception
800
SCI Interrupt Sources and DMAC
801
Usage Notes
802
Table 15.12 SCI Interrupt Sources
802
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
803
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
804
Figure 15.25 Example of Synchronous Transmission by DMAC
805
Figure 15.26 Example Countermeasure on SH7750
807
Figure 15.27 Clock Input Timing of SCK Pin
807
Table 15.14 Peripheral Module Signal Timing
808
Section 16 Serial Communication Interface with FIFO (SCIF)
809
Overview
809
Features
809
Block Diagram
811
Figure 16.1 Block Diagram of SCIF
811
Pin Configuration
812
Table 16.1 SCIF Pins
812
Register Configuration
813
Register Descriptions
813
Receive Shift Register (SCRSR2)
813
Table 16.2 SCIF Registers
813
Receive FIFO Data Register (SCFRDR2)
814
Transmit Shift Register (SCTSR2)
814
Transmit FIFO Data Register (SCFTDR2)
815
Serial Mode Register (SCSMR2)
815
Serial Control Register (SCSCR2)
818
Serial Status Register (SCFSR2)
821
Bit Rate Register (SCBRR2)
828
FIFO Control Register (SCFCR2)
829
FIFO Data Count Register (SCFDR2)
833
Serial Port Register (SCSPTR2)
834
Figure 16.2 MD8/RTS2 Pin
837
Figure 16.3 CTS2 Pin
838
Figure 16.4 Md1/Txd2 Pin
839
Figure 16.5 Md2/Rxd2 Pin
839
Line Status Register (SCLSR2)
840
Operation
841
Overview
841
Serial Operation
842
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection
842
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection
842
Table 16.5 Serial Transmit/Receive Formats
843
Figure 16.6 Sample SCIF Initialization Flowchart
845
Figure 16.7 Sample Serial Transmission Flowchart
846
Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
848
Figure 16.9 Example of Operation Using Modem Control (CTS2)
848
Figure 16.10 Sample Serial Reception Flowchart (1)
849
Figure 16.10 Sample Serial Reception Flowchart (2)
850
Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
852
SCIF Interrupt Sources and the DMAC
853
Figure 16.12 Example of Operation Using Modem Control (RTS2)
853
Usage Notes
854
Table 16.6 SCIF Interrupt Sources
854
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
856
Figure 16.14 Overrun Error Flag
858
Section 17 Smart Card Interface
859
Overview
859
Features
859
Block Diagram
860
Figure 17.1 Block Diagram of Smart Card Interface
860
Pin Configuration
861
Register Configuration
861
Table 17.1 Smart Card Interface Pins
861
Table 17.2 Smart Card Interface Registers
861
Register Descriptions
862
Smart Card Mode Register (SCSCMR1)
862
Serial Mode Register (SCSMR1)
863
Serial Control Register (SCSCR1)
864
Serial Status Register (SCSSR1)
865
Operation
866
Overview
866
Pin Connections
867
Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections
867
Data Format
868
Figure 17.3 Smart Card Interface Data Format
868
Register Settings
869
Table 17.3 Smart Card Interface Register Settings
869
Figure 17.4 TEND Generation Timing
870
Clock
871
Figure 17.5 Sample Start Character Waveforms
871
Table 17.4 Values of N and Corresponding CKS1 and CKS0 Settings
872
Table 17.5 Examples of Bit Rate B (Bits/S) for Various SCBRR1 Settings (When N = 0)
872
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (Bits/S) (When N = 0)
872
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
873
Table 17.8 Register Settings and SCK Pin State
873
Data Transmit/Receive Operations
874
Figure 17.6 Difference in Clock Output According to GM Bit Setting
874
Figure 17.7 Sample Initialization Flowchart
875
Figure 17.8 Sample Transmission Processing Flowchart
877
Figure 17.9 Sample Reception Processing Flowchart
879
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
880
Usage Notes
881
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode
881
Figure 17.11 Retransfer Operation in SCI Receive Mode
883
Figure 17.12 Retransfer Operation in SCI Transmit Mode
883
Figure 17.13 Procedure for Stopping and Restarting the Clock
884
Section 18 I/O Ports
887
Overview
887
Features
887
Block Diagrams
888
Figure 18.1 16-Bit Port
888
Figure 18.2 4-Bit Port
889
Figure 18.3 MD0/SCK Pin
890
Figure 18.4 Md7/Txd Pin
891
Figure 18.5 Rxd Pin
891
Figure 18.6 Md1/Txd2 Pin
892
Figure 18.7 Md2/Rxd2 Pin
892
Figure 18.8 CTS2 Pin
893
Figure 18.9 MD8/RTS2 Pin
894
Pin Configuration
895
Table 18.1 20-Bit General-Purpose I/O Port Pins
895
Table 18.2 SCI I/O Port Pins
896
Table 18.3 SCIF I/O Port Pins
896
Register Configuration
897
Table 18.4 I/O Port Registers
897
Register Descriptions
898
Port Control Register a (PCTRA)
898
Port Data Register a (PDTRA)
899
Port Control Register B (PCTRB)
900
Port Data Register B (PDTRB)
901
GPIO Interrupt Control Register (GPIOIC)
902
Serial Port Register (SCSPTR1)
903
Serial Port Register (SCSPTR2)
905
Section 19 Interrupt Controller (INTC)
909
Overview
909
Features
909
Block Diagram
909
Figure 19.1 Block Diagram of INTC
910
Pin Configuration
911
Register Configuration
911
Table 19.1 INTC Pins
911
Table 19.2 INTC Registers
911
Interrupt Sources
912
NMI Interrupt
912
IRL Interrupts
913
Figure 19.2 Example of IRL Interrupt Connection
913
Table 19.3 IRL3-IRL0 Pins and Interrupt Levels
914
On-Chip Peripheral Module Interrupts
915
Table 19.4 SH7750 IRL3-IRL0 Pins and Interrupt Levels (When IRLM = 1)
915
Interrupt Exception Handling and Priority
916
Table 19.5 Interrupt Exception Handling Sources and Priority Order
917
Register Descriptions
919
Interrupt Priority Registers a to D (IPRA-IPRD)
919
Table 19.6 Interrupt Request Sources and IPRA-IPRD Registers
920
Interrupt Control Register (ICR)
921
Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
923
Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
923
Interrupt Source Register 00 (INTREQ00) (SH7750R Only)
924
Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)
925
Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)
926
Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only)
926
Table 19.8 Bit Assignments
926
INTC Operation
927
Interrupt Operation Sequence
927
Figure 19.3 Interrupt Operation Flowchart
928
Multiple Interrupts
929
Interrupt Masking with MAI Bit
929
Interrupt Response Time
930
Table 19.9 Interrupt Response Time
930
Usage Notes
931
NMI Interrupts (SH7750 and SH7750S Only)
931
Section 20 User Break Controller (UBC)
935
Overview
935
Features
935
Block Diagram
936
Figure 20.1 Block Diagram of User Break Controller
936
Table 20.1 UBC Registers
937
Register Descriptions
938
Access to UBC Control Registers
938
Break Address Register a (BARA)
939
Break ASID Register a (BASRA)
940
Break Address Mask Register a (BAMRA)
940
Break Bus Cycle Register a (BBRA)
941
Break Address Register B (BARB)
943
Break ASID Register B (BASRB)
943
Break Address Mask Register B (BAMRB)
943
Break Data Register B (BDRB)
943
Break Data Mask Register B (BDMRB)
944
Break Bus Cycle Register B (BBRB)
945
Break Control Register (BRCR)
945
Operation
948
Explanation of Terms Relating to Accesses
948
Explanation of Terms Relating to Instruction Intervals
948
User Break Operation Sequence
949
Instruction Access Cycle Break
950
Operand Access Cycle Break
951
Condition Match Flag Setting
952
Program Counter (PC) Value Saved
952
Contiguous a and B Settings for Sequential Conditions
953
Usage Notes
954
User Break Debug Support Function
956
Figure 20.2 User Break Debug Support Function Flowchart
957
Examples of Use
958
User Break Controller Stop Function
960
Transition to User Break Controller Stopped State
960
Cancelling the User Break Controller Stopped State
960
Examples of Stopping and Restarting the User Break Controller
961
Section 21 High-Performance User Debug Interface (H-UDI)
963
Overview
963
Features
963
Block Diagram
963
Figure 21.1 Block Diagram of H-UDI Circuit
964
Pin Configuration
965
Table 21.1 H-UDI Pins
965
Register Configuration
966
Table 21.2 H-UDI Registers
966
Register Descriptions
967
Instruction Register (SDIR)
967
Data Register (SDDR)
969
Bypass Register (SDBPR)
969
Interrupt Source Register (SDINT) (SH7750R Only)
970
Boundary Scan Register (SDBSR) (SH7750R Only)
971
Table 21.3 Configuration of the Boundary Scan Register
972
Operation
975
TAP Control
975
Figure 21.2 TAP Control State Transition Diagram
975
H-UDI Reset
976
H-UDI Interrupt
976
Figure 21.3 H-UDI Reset
976
Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)
977
Usage Notes
977
Section 22 Electrical Characteristics
979
Absolute Maximum Ratings
979
Table 22.1 Absolute Maximum Ratings
979
DC Characteristics
980
Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V))
980
Table 22.3 DC Characteristics (HD6417750RF240 (V))
982
Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V))
984
Table 22.5 DC Characteristics (HD6417750RF200 (V))
986
Table 22.6 DC Characteristics (HD6417750SBP200 (V))
988
Table 22.7 DC Characteristics (HD6417750SF200 (V))
990
Table 22.8 DC Characteristics (HD6417750BP200M (V))
992
Table 22.9 DC Characteristics (HD6417750SF167 (V))
994
Table 22.10 DC Characteristics (HD6417750F167 (V))
996
Table 22.11 DC Characteristics (HD6417750SVF133 (V))
998
Table 22.12 DC Characteristics (HD6417750SVBT133 (V))
1000
Table 22.13 DC Characteristics (HD6417750VF128 (V))
1002
Table 22.14 Permissible Output Currents
1003
AC Characteristics
1004
Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V))
1004
Table 22.16 Clock Timing (HD6417750RF240 (V))
1004
Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V))
1004
Table 22.18 Clock Timing (HD6417750RF200 (V))
1004
Table 22.19 Clock Timing (HD6417750SF200 (V))
1005
Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V))
1005
Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V))
1005
Table 22.22 Clock Timing (HD6417750VF128 (V))
1005
Clock and Control Signal Timing
1006
Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V))
1006
Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V))
1008
Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V))
1010
Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V))
1012
Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V))
1014
Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V))
1016
Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V)
1018
Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V))
1020
Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V))
1022
Figure 22.1 EXTAL Clock Input Timing
1024
Figure 22.2 (1) CKIO Clock Output Timing
1024
Figure 22.2 (2) CKIO Clock Output Timing
1024
Figure 22.3 Power-On Oscillation Settling Time
1025
Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET)
1025
Figure 22.5 Power-On Oscillation Settling Time
1026
Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET)
1026
Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI)
1027
Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0)
1027
Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt
1028
Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt
1028
Figure 22.11 Manual Reset Input Timing
1029
Figure 22.12 Mode Input Timing
1029
Control Signal Timing
1030
Table 22.32 Control Signal Timing (1)
1030
Table 22.32 Control Signal Timing (2)
1031
Figure 22.13 Control Signal Timing
1032
Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode
1032
Figure 22.14 (2) Pin Drive Timing for Software Standby Mode
1033
Bus Timing
1034
Table 22.33 Bus Timing (1)
1034
Table 22.33 Bus Timing (2)
1036
Table 22.33 Bus Timing (3)
1038
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (no Wait)
1040
Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
1041
Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
1042
Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
1043
Figure 22.19 Burst ROM Bus Cycle (no Wait)
1044
Figure 22.20 Burst ROM Bus Cycle
1045
Figure 22.21 Burst ROM Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
1046
Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
1047
Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, cas Latency = 3, TPC[2:0] = 011)
1048
Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, cas Latency = 3, TPC[2:0] = 011)
1049
Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, cas Latency = 3)
1050
Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, cas Latency = 3)
1051
Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst ((RASD = 1, cas Latency = 3)
1052
Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
1053
Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
1054
Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010)
1055
Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)
1056
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010)
1057
Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (RASD = 1, TPC[2:0] = 001)
1058
Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (tras = 1, TRC[2:0] = 001)
1059
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001)
1060
Figure 22.36 (A) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)
1061
Figure 22.36 (B) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register
1062
Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0]
1063
Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
1064
Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
1065
Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
1066
Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001, 2-Cycle cas Negate Pulse Width)
1067
Figure 22.42 DRAM Burst Bus Cycle: RAS down Mode State
1068
Figure 22.43 DRAM Burst Bus Cycle: RAS down Mode Continuation (EDO Mode, RCD[1:0] = 00, Anw[2:0] = 000)
1069
Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000, TPC[2:0] = 001)
1070
Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001)
1071
Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, Anw[2:0] = 001, TPC[2:0] = 001, 2-Cycle cas Negate Pulse Width)
1072
Figure 22.47 DRAM Burst Bus Cycle: RAS down Mode State (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
1073
Figure 22.48 DRAM Burst Bus Cycle: RAS down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, Anw[2:0] = 000)
1074
Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
1075
Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001)
1076
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)
1077
Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
1078
Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, no Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait
1079
Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing)
1080
Figure 22.55 MPX Basic Bus Cycle: Read (1) 1St Data (One Internal Wait) (2) 1St Data
1081
Figure 22.56 MPX Basic Bus Cycle: Write (1) 1St Data (no Wait) (2) 1St Data
1082
Figure 22.58 MPX Bus Cycle: Burst Write (1) no Internal Wait (2) 1St Data (One Internal Wait), 2Nd to 4Th Data (no Internal Wait + External Wait Control)
1084
Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (no Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait)
1085
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (no Wait, Address Setup/Hold Time Insertion, Ans[0] = 1, Anh[1:0] =0 1)
1086
Peripheral Module Signal Timing
1087
Table 22.34 Peripheral Module Signal Timing (1)
1087
Table 22.34 Peripheral Module Signal Timing (2)
1089
Table 22.34 Peripheral Module Signal Timing (3)
1091
Table 22.34 Peripheral Module Signal Timing (4)
1092
Table 22.34 Peripheral Module Signal Timing (5)
1094
Figure 22.61 TCLK Input Timing
1095
Figure 22.62 RTC Oscillation Settling Time at Power-On
1095
Figure 22.63 SCK Input Clock Timing
1095
Figure 22.64 SCI I/O Synchronous Mode Clock Timing
1096
Figure 22.65 I/O Port Input/Output Timing
1096
Figure 22.66 (A) DREQ/DRAK Timing
1096
Figure 22.66 (B) DBREQ/TR Input Timing and BAVL Output Timing
1097
Figure 22.67 TCK Input Timing
1097
Figure 22.68 RESET Hold Timing
1098
Figure 22.69 H-UDI Data Transfer Timing
1098
Figure 22.70 Pin Break Timing
1098
Figure 22.71 NMI Input Timing
1098
AC Characteristic Test Conditions
1099
Figure 22.72 Output Load Circuit
1099
Delay Time Variation Due to Load Capacitance
1100
Figure 22.73 Load Capacitance Vs. Delay Time
1100
Appendix A Address List
1101
Table A.1 Address List
1101
Appendix B Package Dimensions
1107
Figure B.1 Package Dimensions (256-Pin BGA)
1107
Figure B.2 Package Dimensions (208-Pin QFP)
1108
Figure B.3 Package Dimensions (264-Pin CSP)
1109
Figure B.4 Package Dimensions (292-Pin BGA)
1110
Appendix C Mode Pin Settings
1111
Appendix D CKIO2ENB Pin Configuration
1115
Figure D.1 CKIO2ENB Pin Configuration
1115
Appendix E Pin Functions
1117
Pin States
1117
Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State
1117
Handling of Unused Pins
1120
Appendix F Synchronous DRAM Address Multiplexing Tables
1121
Appendix G Prefetching of Instructions and Its Side Effects
1143
Figure G.1 Instruction Prefetch
1143
Appendix H Power-On and Power-Off Procedures
1145
Power-On Stipulations
1145
Power-Off Stipulations
1145
Common Stipulations for Power-On and Power-Off
1146
Appendix I Product Lineup
1149
Appendix J Version Registers
1151
Index
1153
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