Pll Selection; Digital Audio Connections And Routing - Analog Devices ADAU1962 User Manual

Evaluation Board User Guide

PLL SELECTION

The PLL in the ADAU1962/ADAU1966
allowing the part to run from a wide range of either MCLK or
LRCLK frequencies. It is also possible to shut the PLL off
altogether and use the part in direct MCLK mode; functionality
with no PLL is limited to 256 × f
By default, the ADAU1962/ADAU1966
MCLK as the clock source. The MCLK loop filter must be
selected using JP2, as shown in Figure 14.
Figure 14. MCLK Selection for PLL Loop Filter
DLRCLK can be selected as the PLL clock source using the PLL
and Clock Control Register 0, Register 0x00, Bits[7:6]. In this
case, the LRCLK loop filter must be selected, as shown in Figure 15.
If DLRCLK is selected as the PLL clock, there is no need for an
MCLK signal.
Figure 15. LRCLK Selection for PLL Loop Filter

DIGITAL AUDIO CONNECTIONS AND ROUTING

The ADAU1962/ADAU1966
inputs for digital audio signals: S/PDIF and SDP interface.
The S/PDIF receiver can handle either of two options: COAX
uses the RCA jack, J1, and OPT uses the Toslink jack, U1. The
S/PDIF input is selected using S1, as shown in Figure 16.
is very flexible,
.
S
run from the PLL using
evaluation board has two separate
Figure 16. S/PDIF Input Selector Switch, SW1
A series of resistors is provided to set the functional mode of the
S/PDIF receiver. By default, the S/PDIF receiver runs in master
mode, 256 × f , I
S
receiver to make changes to the hardware mode.
The jumpers shown in Figure 17 are set for the S/PDIF receiver
to drive the DBCLK and DLRCLK clock ports and the eight
DSDATAx lines of the ADAU1962/ADAU1966. JP22 selects the
input to the buffer; the output of this buffer shows up on the right-
hand column of JP13 to JP20. The pins in the middle column of
these jumpers are connected to the DSDATAx pins of the
ADAU1962/ADAU1966
DBCLK and DLRCLK selections are made with JP10 and JP12,
respectively, where the middle pins are connected to the
DBCLK and DLRCLK pins of the ADAU1962/ADAU1966.
Figure 17. S/PDIF Data and Clock Routing
The SDP interface, J6 and J8, make up a standard interconnect
within Analog Devices. They provide for transfer of digital audio,
clocks, and control between boards. For additional information,
see the pinout included in the schematic in Figure 28.
Rev. A | Page 7 of 28
2 S format; consult the data sheet for the S/PDIF
through the appropriate line termination.
UG-416