Jesd204B Lane Mapping Of The Evaluation Board - Analog Devices AD9161 User Manual

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JESD204B LANE MAPPING OF THE EVALUATION
BOARD
The ADS7-V2EBZ is based on a Xilinx® Virtex7 FPGA device.
The user can configure another Xilinx Virtex7-based evaluation
board to drive the AD9161 series evaluation board. The
JESD204B parameters are available in the AD9161, AD9162,
AD9163, and AD9164 data sheets.
The physical lanes on the FMC connector are not necessarily
connected to the same lanes on the AD9161, AD9162, AD9163,
and AD9164. The AD9161, AD9162, AD9163, and
have a cross bar switch on the JESD204B link. However, in the
case of the ADS7-V2EBZ, AD9161, AD9162, AD9163, and
AD9164, mapping is done using the cross bar in the Xilinx
JESD204B transmitter.
The following list is the mapping between the FMC lanes and
the AD9161, AD9162, AD9163, and
evaluation board. The mapping to the Xilinx JESD204B
intellectual property (IP) is also provided in the following list
for reference.
•
Physical Lane 0 on the FMC connector (DP0_C2M) is also
Lane 0 on the AD9161, AD9162, AD9163, and
(Lane 0 the Xilinx JESD204B IP)
•
Physical Lane 1 on the FMC connector (DP1_C2M) is also
Lane 1 on the AD9161, AD9162, AD9163, and
(Lane 1 out of the Xilinx JESD204B IP)
•
Physical Lane 2 on the FMC connector (DP2_C2M) is also
Lane 2 on the AD9161, AD9162, AD9163, and
(Lane 2 out of the Xilinx JESD204B IP)
•
Physical Lane 3 on the FMC connector (DP3_C2M) is also
Lane 3 on the AD9161, AD9162, AD9163, and
(Lane 3 out of the Xilinx JESD204B IP)
AD9164
AD9164 lanes on the
AD9164
AD9164
AD9164
AD9164
Figure 21. Record Length in 3-Lane/6-Lane Mode
Rev. 0 | Page 18 of 22
AD9161/AD9162/AD9163/AD9164
•
Physical Lane 4 on the FMC connector (DP4_C2M) is
Lane 5 on the AD9161, AD9162, AD9163, and
(Lane 5 out of the Xilinx JESD204B IP)
•
Physical Lane 5 on the FMC connector (DP5_C2M) is
Lane 7 on the AD9161, AD9162, AD9163, and
(Lane 7 out of the Xilinx JESD204B IP)
•
Physical Lane 6 on the FMC connector (DP6_C2M) is also
Lane 6 on the AD9161, AD9162, AD9163, and
(Lane 6 out of the Xilinx JESD204B IP)
•
Physical Lane 7 on the FMC connector (DP7_C2M) is
Lane 4 on the AD9161, AD9162, AD9163, and
(Lane 4 out of the Xilinx JESD204B IP)
There is also input data pin polarity (positive/negative (P/N))
inversion between the transmitter and receiver on the evaluation
board to ease layout. The polarity can easily be inverted in the
Xilinx physical layer by inverting Physical Lane 4 to Lane 7
(DP4_C2M to DP7_C2M) on the FMC connector (P/N swapped).
When the JESD204B is running, the following are a few debug
ideas. Monitor the sync lane.
•
If the sync lane stays low, the JESD204B reference
frequency needs to be adjusted.
•
Sync lane toggles: P/N lanes needs to be adjusted. Otherwise,
with inverted polarity, K character passes, but initial lane
alignment sequence (ILAS) does not pass, creating sync
signal toggling.
•
Sync stays high, but output spectrum is not valid.
Transport or mapping of lane is wrong.
Note that in 3-lane or 6-lane mode, single-tone record length is
multiples of 3. Otherwise, the output spectrum is not correct.
An example is shown in Figure 21.
User Guide
AD9164
AD9164
AD9164
AD9164