Power Stage Board Description; Analog Control Board Description - Analog Devices AD8450-EVALZ User Manual

UG-845

POWER STAGE BOARD DESCRIPTION

Figure 17 shows the power stage board schematic. The bench
power supply connects to the power stage board through the
J2 (+) and J4 (−) banana jacks. The J3 (+) and J4 (−) banana
jacks are the regulated charge/discharge terminals, and connect
to an electronic load or battery.
The power stage includes input capacitors, a low-side and high-
side MOSFET, an inductor, and output capacitors. Depending
on the mode of operation, the
either in step-down (buck) or step-up (boost) mode. The board
includes pads for up to two parallel MOSFETs and up to two
parallel dual diodes. The ADP1972
nonsynchronous mode. Therefore, having external, low forward
voltage diodes in parallel with the MOSFETs is very important
for operation at high efficiency.
The power stage board includes a 2 mΩ sense resistor (R1) for
measuring the output current to the electronic load or battery.
The ADuM7223 translates the 5 V level PWM signals from the
ADP1972 into low impedance, 10 V drive signals for the
MOSFETs. An auxiliary step-down regulator based on the
ADP2441 generates the 10 V rail for the MOSFET driver from
the main input rail.
ADP1972 drives the power stage
drives the power stage in
AD8450-EVALZ/ADP1972-EVALZ User Guide

ANALOG CONTROL BOARD DESCRIPTION

The analog control board includes the ADP1972, the AD8450/
AD8451, a DAC to configure the set points, and an ADC to
monitor the current and voltage.
The analog control board includes an
to generate 5 V, and an
that generates −5 V for the
measure and output voltages close to 0 V.
The current sense programmable gain instrumentation amplifier
(PGIA) of the AD8450
populating R18 and R29. Table 2 shows how to configure the
board to achieve other gains. With a gain of 66, a 20 A output
current results in an output voltage of 2.64 V at TP4 (ISMEA pin).
The voltage sense programmable gain different amplifier
(PGDA) is configured for a gain of 0.8 by populating R41 and
R42. Table 3 shows how to configure the board for other
possible gains. With a gain of 0.8, a 5 V battery voltage results in
a 4 V output at TP1 (BVMEA pin).
Table 2. PGIA Gain Configuration
Gain Resistors with 0 Ω jumpers
26 R19, R30
66 R18, R29
133 R17, R28
200 R16, R27
Table 3. PGDA Gain Configuration
Gain Resistors with 0 Ω jumpers
0.8 R41, R42
0.4 R40, R43
0.27 R39, R44
0.2 R38, R45
The AD7173-8
and reports the values to the user interface software through the
SDP-S interface. The full-scale input range of the
5 V. The AD5689R
current setpoint, and Output B sets the constant voltage
setpoint. The DAC output range is also from 0 V to 5 V. Given
the current and voltage gain settings of the AD8450/AD8451,
the current and voltage setpoints can be calculated as follows:
Constant_Current_Setpoint = V
Constant_Current_Setpoint = V
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ADP7102
ADM8829 switched capacitor inverter
AD8450/AD8451
is configured for a gain of 66 by
ADC measures the voltage and current signals
DAC Output A configures the constant
/(PGIA_GAIN × 0.003)
DAC_A
/(PGDA_GAIN)
DAC_B
linear regulator
so that it can
AD7173-8 is