Holtek HT827A0 Manual page 15

WDT prescaler, a longer time-out period can be
attained. Writing data to WS2, WS1 and WS0
(bits 2, 1 and 0 of WDTS) can derive different
time-out periods. If WS2, WS1 and WS0 are all
equal to 1, the division ratio is up to 1:128, and
the maximum time-out period is 2.6 seconds.
WS2 WS1 WS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
WDTS register
If the WDT oscillator is disabled, the WDT clock
may still come from an instruction clock. It oper-
ates in the same manner except that WDT may
stop counting and loses its protecting purpose in
the HALT state. In this situation the logic can
only be re-initialized by external logic. The high
nibble and bit 3 of WDTS are reserved for user¢s
defined flags. The programmer may use these
flags to indicate some specified statuses.
The on-chip RC oscillator (WDT OSC) is
strongly recommended if the device operates in
a noisy environment, since the HALT function
will stop the system clock.
Overflow of the WDT under a normal operation
initializes a ²chip reset² and sets the status bit
²TO². It will initialize a ²warm reset², and only
PC and SP are reset to zero in the HALT mode.
S y s t e m C l o c k / 4
W D T
O S C
To clear the contents of WDT (including the
WDT prescaler), three methods are adopted,
namely, external reset (a low level to RES),
software instructions, and ²HALT² instruction.
The software instructions include ²CLR WDT²
and the other sets - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, by
Division Ratio
mask option only one can be active at a time -
1:1
²CLR WDT times selection option². If ²CLR
1:2
WDT² is chosen (i.e., CLRWDT times equal
one), any execution of the ²CLR WDT² instruc-
1:4
tion will clear WDT. In the case that ²CLR
1:8
WDT1² and ²CLR WDT2² are selected (i.e.,
1:16
CLRWDT times equal two), these two instruc-
tions must be executed to clear WDT; otherwise
1:32
WDT may reset the chip as a result of time-out.
1:64
1:128
Power down operation - HALT
The HALT mode is initialized by the ²HALT²
instruction and results in the following:
· The system oscillator is turned off but the
WDT oscillator still keeps running (if the
WDT oscillator is selected).
· The contents of the on-chip RAM and regis-
ters remain unchanged.
· The WDT and WDT prescaler are cleared and
re-counted (if the clock of WDT is from the
WDT oscillator).
· All the I/O ports maintain their original
statuses.
· The PD flag is set and the TO flag cleared.
The system can quit the HALT mode by an exter-
nal reset, interrupt, external falling edge signal
on port A or WDT overflow. An external reset
leads to device initialization and a WDT overflow
performs a ²warm reset². The reason for chip re-
M a s k
8 - b i t C o u n t e r
O p t i o n
S e l e c t i o n
Watchdog timer
15
W D T P r e s c a l e r
7 - b i t C o u n t e r
8 - t o - 1 M U X
W S 0 ~ W S 2
W D T T i m e - o u t
March 15, 2000
HT827A0