Holtek HT827A0 Manual

8-bit microcontroller with voice rom

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Features

8-bit microcontroller

Operating voltage: 2.4V~5.2V

8K´16 program ROM

208´8 data RAM

36 bidirectional I/O lines

Interrupt input

16-bit programmable timer/event

counter with overflow interrupts

Watchdog timer

On-chip crystal or RC types of oscillator

Voice and melody synthesizer

128K´8 voice ROM

3/4 bit ADPCM coding algorithm

26 kinds of voice sampling rates

Tone level of 4 octaves

14 kinds of melody beats

Applications

Intelligent educational toys

High end toy controllers

Talking alarm clocks

General Description

The HT827A0 is 8-bit high performance

microcontroller with a voice synthesizer and

tone generator. They are designed for applica-

tions on multiple I/Os with sound effects. The

LSIs provide 26 kinds of voice sampling rates, 4

octaves of tone level as well as a high quality of

8-Bit Microcontroller with Voice ROM

Halt function and wake-up feature reduces

power consumption

63 powerful instructions

Up to a 1ms instruction cycle with a 4MHz

system clock at V

All instructions in 1 or 2 machine cycles

16-bit table read instruction

8-level subroutine nesting

Bit manipulation instruction

Current type of D/A switch output

Tone generator counter

Controllable volume

48-pin DIP package

Alert and warning systems

Public address systems

Sound effect generators

current type D/A output. With such a flexible

structure, the HT827A0 is excellent for versa-

tile voice and sound effect product applications.

It also includes a halt function to reduce power

consumption.

HT827A0

=5V

March 15, 2000

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Summary of Contents for Holtek HT827A0

Page 1 The HT827A0 is 8-bit high performance current type D/A output. With such a flexible microcontroller with a voice synthesizer and structure, the HT827A0 is excellent for versa- tone generator. They are designed for applica- tile voice and sound effect product applications.
Page 2: Block Diagram
HT827A0 Block Diagram I N T T M R V o i c e R O M O S C 1 & C o n t r o l l e r 8 - b i t H i g h P e r f o r m a n c e...
Page 3: Pad Assignment
HT827A0 Pad Assignment P B 3 P B 2 P B 1 P B 0 V S S P E 0 P E 1 P E 2 P E 3 ( 0 , 0 ) I N T T M R...
Page 4: Pad Coordinates
HT827A0 Pad Coordinates Unit: mm Pad No. Pad No. -1543.05 2242.95 69.05 -2211.75 1675.25 237.85 -1486.75 -2211.75 -1486.75 1491.25 598.35 -2291.45 -1486.75 1308.95 890.95 -2291.45 1126.15 1184.35 -1486.75 -2291.45 -1486.75 925.35 1476.95 -2291.45 -1486.75 727.25 1507.85 -2091.35 -1486.75 538.35 1499.05 -1925.15...
Page 5: Absolute Maximum Ratings
HT827A0 Mask Pad No. Pad Name I/O Description Option Bidirectional 8-bit input/output ports Pull-high Software instructions determine the CMOS output or 13~20 PD0~PD7 or None schmitt trigger input with or without a pull-high resistor (mask option). Negative power supply, ground ¾...
Page 6 HT827A0 D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage ¾ ¾ ¾ ¾ No load, Operating Current (Crystal OSC) =4MHz ¾ ¾ No load, Operating Current (RC OSC) =4MHz ¾ ¾ ¾ No load,...
Page 7 HT827A0 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 4000 ¾ ¾ System Clock (Crystal OSC) SYS1 ¾ ¾ 4000 ¾ ¾ 4000 System Clock (RC OSC) SYS2 ¾ ¾ 4000 ¾ ¾ 4000 Timer I/P Frequency (TMR) TIMER ¾...
Page 8: Functional Description
Executive flow containing the next instruction code. The HT827A0 provides a system clock which is The PC manipulates a program transfer by derived from a crystal or an RC type of oscillator.
Page 9 T i m e r / e v e n t c o u n t e r i n t e r r u p t s u b r o u t i n e The program memory size for HT827A0 is...
Page 10 TBLP before accessing the table. All the table to, some are read only. related instructions require 2 cycles to com- The data memory size for HT827A0 is shown as plete an operation. These areas may function follows. as a normal program memory depending upon the user¢s requirements.
Page 11 HT827A0 control registers (PAC; 13H, PBC; 15H, PCC; I n d i r e c t A d d r e s s i n g R e g i s t e r 0 0 H 17H, PDC; 19H, PEC; 1BH). The 20H to 2FH 0 1 H are used for sound and tone (melody) synthesis.
Page 12 HT827A0 Interrupt Status register - STATUS The HT827A0 provides an external interrupt in This 8-bit register (0AH) consists of a zero flag addition to two internal timer/event counter in- (Z), carry flag (C), auxiliary carry flag (AC), terrupts. The interrupt control register (INTC;...
Page 13 HT827A0 stack and then branching to subroutines at the The internal timer/event counter interrupt is specified location(s) in the program memory. initialized by setting a timer/event counter in- Only the program counter is pushed onto the terrupt request flag (TF; bit 6 of INTC), which stack.
Page 14 Watchdog timer - WDT Oscillator configuration The clock source of WDT is implemented by a The HT827A0 provides two kinds of oscillator cir- dedicated RC oscillator (WDT oscillator) or in- struction clock (system clock divided by 4), de- cuits, namely, RC and crystal oscillators, for sys- cided by mask option.
Page 15 HT827A0 WDT prescaler, a longer time-out period can be To clear the contents of WDT (including the attained. Writing data to WS2, WS1 and WS0 WDT prescaler), three methods are adopted, (bits 2, 1 and 0 of WDTS) can derive different namely, external reset (a low level to RES), time-out periods.
Page 16: Reset Conditions
(system clock period) to resume a normal opera- the HALT state or from system power-up and tion. In other words, the HT827A0 will insert a the RES transforms low to high. XST is auto- dummy period after the wake-up. If the system...
Page 17 R E S Reset circuit Audio output and volume control The HT827A0 provides a current type D/A out- put for driving external 8W speaker through an external NPN transistor. The user must write the voice data to the register DAL (20H) and DAH (21H).
Page 18 HT827A0 The states of the registers are summarized in the following table: WDT Time-out RES Reset Reset RES Reset Time-out Register (Normal (Normal (Power On) (HALT) Operation) Operation) (HALT)* TMRH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu...
Page 19 HT827A0 Sampling rate counter Code Freq. Code Freq. The HT827A0 offers a sampling rate counter. xx00 1010 5.08kHz xx01 0111 12.43kHz This counter contains a 5 bit programmable xx00 1011 5.33kHz xx01 1000 13.98kHz count-up counter. The clock may come from 128kHz or 2kHz by code option and the clock xx00 1100 5.59kHz...
Page 20 Timer/event counter terrupt request flag (SRF; bit 5 of INTC) if over- The HT827A0 provides a timer/event counter. flow of the divide-by-1 counter occurs. This timer contains an 8-bit/16-bit programma- To enable a counting operation, the ON bit ble count-up counter.
Page 21 HT827A0 TMRH will write the data and the content of the cycle can be measured till TON is set. The cycle low byte buffer into the timer/event counter measurement will go on functioning as long as preload register (16-bit) simultaneously. The further transient pulses are received.
Page 22 TMRC register Tone and melody generator D A T A B U S The HT827A0 provides a tone frequency register (TONE; 2AH), beat frequency register (BEAT; T o n e R e g i s t e r 28H) as well as tempo frequency register (TEMPO;...
Page 23 HT827A0 Code Frequency Tone Code Frequency Tone 1x00 0000 ¾ ¾ 1x10 0000 ¾ ¾ 1x00 0001 138.5Hz 1x10 0001 553.8Hz 1x00 0010 146.4Hz 1x10 0010 585.7Hz 1x00 0011 155.4Hz 1x10 0011 621.5Hz 1x00 0100 164.5Hz 1x10 0100 658.1Hz 1x00 0101 174.8Hz...
Page 24 HT827A0 Code Beat Labels Bits Function 1xxx xxxx Beat time-out To define the tempo frequency TN0~ (refer to the tempo frequency 0000 0000 1/24 Beat table) 0000 0010 1/8 Beat ¾ 4,5 Unused bits, read as ²0² 0000 0011 1/6 Beat...
Page 25 TEMPO.7 (melody) sources are coded by Holtek¢s tools. MOV A, 00H The voice ROM size for HT827A0 is 128K´8. MOV [ROMC], A; Write the first nibble The handshaking between the microcontroller...
Page 26: Input/Output Ports
13H, 15H, 17H, 19H, 1BH. The PE Input/Output ports hi-nibble bits are void, this four bits are read as The HT827A0 includes 36 bidirectional in- ²0². put/output lines, labeled from PA to PC or PE These input/output lines stay at a high level or...
Page 27 HT827A0 Mask option The following table illustrates 5 kinds of mask option in the HT827A0. All of them have to be defined to ensure a proper functioning system. Mask Option OSC type selection This option determines the selection of a system clock, whether an RC or crystal type of oscillator.
Page 28: Application Circuits
HT827A0 Application Circuits RC oscillator for multiple I/O applications Crystal oscillator for multiple I/O applications 2 0 p F O S C O S C 1 O S C 1 P A 0 ~ P A 7 P A 0 ~ P A 7...
Page 29: Logic Operation
HT827A0 Instruction Set Summary Mnemonic Description Flag Affected Arithmetic ADD A,[m] Add data memory to ACC Z,C,AC,OV ADDM A,[m] Add ACC to data memory Z,C,AC,OV ADD A,x Add immediate data to ACC Z,C,AC,OV ADC A,[m] Add data memory to ACC with carry...
Page 30 HT827A0 Mnemonic Description Flag Affected Data Move MOV A,[m] Move data memory to ACC None MOV [m],A Move ACC to data memory None MOV A,x Move immediate data to ACC None Bit Operation CLR [m].i Clear bit of data memory None SET [m].i...
Page 31: Instruction Definition
HT827A0 Instruction Definition ADC A,[m] Add data memory and carry to accumulator Description The contents of the specified data memory accumulator and carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) ¾...
Page 32 HT827A0 ADDM A,[m] Add accumulator to data memory Description The contents of the specified data memory and accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) ¾ ¾ ¾ ¾ Ö Ö...
Page 33 HT827A0 CALL addr Subroutine call Description The instruction unconditionally calls a subroutine which is located at the in- dicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded.
Page 34 HT827A0 CLR WDT1 Preclear watchdog timer Description The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count from zero) if the other preclear WDT instruction has been executed. Execu- tion only of this instruction without the other preclear instruction sets the indicated flag, which implies that this instruction is executed and the PD and TO flags remain unchanged.
Page 35 HT827A0 CPLA [m] Complement data memory place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s comple- ment). Bits which previously contained a one are changed to zero and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
Page 36 HT827A0 DECA [m] Decrement data memory place result in the accumulator Description Data in the specified data memory are decremented by one, leaving the re- sult in the accumulator. The contents of the data memory remain un- changed. Operation ACC ¬ [m]-1 Affected flag(s) ¾...
Page 37 HT827A0 JMP addr Direct Jump Description Bits 0~10 of the program counter are unconditionally replaced with the di- rectly-specified addresses, and the control is passed to this destination. Operation PC ¬ addr Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾...
Page 38 HT827A0 No operation Description No operation is performed. Execution continues with the next instruction. Operation PC ¬ PC+1 Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memory) perform a bitwise logical_OR operation.
Page 39 HT827A0 Return from subroutine Description The program counter is restored from the stack. This is a two-cycle instruc- tion. Operation PC ¬ Stack Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator...
Page 40 HT827A0 RLA [m] Rotate data memory to the left - then place result in the accumulator Description Data in the specified data memory are rotated 1-bit to the left with bit 7 ro- tated into bit 0, leaving the rotation result in the accumulator. The contents of the data memory remain unchanged.
Page 41 HT827A0 RR [m] Rotate data memory to the right Description The contents of the specified data memory are rotated 1-bit to the right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬...
Page 42 HT827A0 RRCA [m] Rotate to the right through carry - then place result in the accumulator Description Data of the specified data memory and carry flag are rotated one bit right. Bit 0 replaces the carry bit and the original carry flag is rotated to the bit 7 posi- tion.
Page 43 HT827A0 SDZ [m] Skip if decrement data memory is zero Description The contents of the specified data memory are decremented by one. If the re- sult is zero, the next instruction is skipped and the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction.
Page 44 HT827A0 SIZ [m] Skip if increment data memory is zero Description The contents of the specified data memory are incremented by one. If the re- sult is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper in- struction.
Page 45 HT827A0 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) ¾ ¾ ¾ ¾ Ö...
Page 46 HT827A0 SWAPA [m] Swap data memory - then place result in the accumulator description The low-order and high-order nibbles of the specified data memory are inter- changed, writing the result to the accumulator. The contents of the data memory remain unchanged.
Page 47 HT827A0 SZ [m].i Skip if bit ²i² of the data memory is zero Description If bit ²i² of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Oth- erwise proceed to the next instruction.
Page 48 HT827A0 XORM A,[m] Logical XOR data memory with accumulator Description Data in the indicated data memory and accumulator perform a bitwise logi- cal Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) ¾...
Page 49 Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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