Table 1: I/O Map - Connect Tech ComSync/104 User Manual

I/O Address Function
(Offset) Name
0 Channel(A)
[1]
Data
1 Channel(A)
[1]
Control
2 Channel(B)
[1]
Data
3 Channel(B)
[1]
Control
4 Status and
Control
5 TC &
Security
6 85230
Control
7 Misc
Control
[8]
8 IRQ
Control
[8]
RS485
9
Control
[6]
0x20 » 0x2F Channel(A)
Registers
[6]
Channel(B)
0x30 » 0x3F
Registers
Notes
[1]
See Zilog ESCC user manual for description of functionality.
[2]
DTR control from this I/O point is only valid when the /DTR//REQ pin of the ESCC is
programmed for use as a DMA request.
[3]
TC is the Terminal Count signal from the PC/104 Bus, which occurs at the end of a
DMA transfer.
[4]
When the /W//REQ pin of the ESCC is programmed as a WAIT function, this bit
enables WAIT states to occur on the PC/104 Bus. When both channels are programmed
to operate in DMA mode, this bit becomes a TC Interrupt Enable.
[5]
85230 Registers bits which are cloned.
[6]
Only when Enhanced Addressing mode is enabled.
[7]
Refer to description below for bit meanings.
[8]
I/O Offsets [8] and [9] are only available on Revision C (or later) cards.
[9]
IRQ Selection can be set at I/O Offset [8] and [4] (same bit numbers).
[10]
Master Interrupt Enable can be set at I/O Offset [8] and [7] (same bit number).
[11]
Software IRQ will cause the card to generate an IRQ and is mostly used for testing.

Table 1: I/O Map

Bit Definitions
(Write)
0 » 7 85230 Data register
0 » 7 85230 Control register
0 » 7 85230 Data register
0 » 7 85230 Control register
[2]
0 DTR(A)
1
DTR(B)
2 Security Feature Enable
3 » 5
IRQ Selection
6 DMA Enable (B)
7
DMA Enable (A)
any Clear TC Interrupt
any Resets 85230 and
Register Bit Clones
0 » 2 Line Interface Mode (A)
3 » 5 Line Interface Mode (B)
6 Master Interrupt Enable
[4]
7
WAIT/TC Enable
0 Shared IRQ Enable
1 IRQ Pull-Down Enable
2 Reserved
[9]
3 » 5
IRQ Selection
6
Master Interrupt Enable
[11]
7
Software IRQ
0 » 3
RX and TX RS485 Modes
4 » 7 Reserved
0 » 7 Register Write data
0 » 7 Register Write data
Bit Definitions
0 » 7 85230 Data register
0 » 7 85230 Control register
0 » 7 85230 Data register
0 » 7 85230 Control register
0 DSR(A)
1 DSR(B)
2 Security Feature Enable
3 85230 INT pin
4 I/O mode
5
TC Interrupt
6 DMA Enable (B)
7
DMA Enable (A)
[3]
0 » 7 Security Function
0 » 7 85230 Interrupt Acknowledge
[5]
0 » 2 Line Interface Mode (A)
3 » 5 Line Interface Mode (B)
6 Master Interrupt Enable
7
WAIT/TC Enable
0 Shared IRQ Enable
1 IRQ Pull-Down Enable
2 Reserved
3 » 5 IRQ Selection
[10]
6 Master Interrupt Enable
7 Software IRQ
[7]
0 » 3
RX and TX RS485 Modes
4 » 7 Reserved
0 » 7 Register Read data
0 » 7 Register Read data
(Read)
[3]
[4]
[7]