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Connect Tech FreeForm/PCI-104 User Manual Table of Contents Limited Lifetime Warranty......................2 Copyright Notice ........................2 Trademark Acknowledgment ..................... 2 Customer Support Overview ...................... 3 Contact Information ......................3 Table of Contents ........................4 List of Tables..........................5 List of Figures ..........................5 Introduction ..........................
Connect Tech FreeForm/PCI-104 User Manual Introduction Connect Tech’s FreeForm/PCI-104 features Xilinx’s Virtex-5 multi-platform FPGA offering users a flexible, reconfigurable computing platform that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I/O interfaces.
Connect Tech FreeForm/PCI-104 User Manual System Overview The following conceptual block diagram provides a high level overview of the FreeForm/PCI-104 and illustrates the general interconnection between components and connectors. For the actual orientation and description of components refer to Figure 2 and Table 1 respectively.
Connect Tech FreeForm/PCI-104 User Manual Reference Design The FreeForm/PCI-104 ships with a pre-installed reference design that is loaded into the FPGA’s configuration flash. This reference design demonstrates how to interface the FreeForm/PCI-104 (Virtex-5 FPGA) with the PLX PCI 9056 PCI to Local Bus Bridge, as well as the various peripherals.
Connect Tech FreeForm/PCI-104 User Manual Hardware Description The following sections describe the function of all switches/jumpers and provide details on connector pinouts. Jumpers and Switches Slot Selection (RSW1) This rotary switch selects a slot position in the PCI-104 stack. When mounting on a PCI adapter card, ensure slot one is selected.
Connect Tech FreeForm/PCI-104 User Manual Connector Pinouts PCI-104 Header (P1) Refer to PCI-104 specifications. Note: P1 must be connected to a PCI-104 stack supplying both 3.3V and 5V. JTAG Programming Header (P2) Use P2 to configure the FPGA via JTAG. Refer to FPGA Configuration for more information.
If connecting two FreeForm/PCI-104’s together using the Rocket I/O interface in a cross-over fashion; care must be taken. Ensure that only cables provided by Connect Tech are used. Cables ordered directly from Samtec or a third party could result in damage to the cable and/or the FreeForm/PCI-104 board itself.
Connect Tech FreeForm/PCI-104 User Manual Top View RS-485 Headers (P5, P6) Table 7: RS-485 Port 1 Pinout (P5) Signal Direction RXD+1 Input RXD-1 Input TXD+1 Output 485 Port 0 TXD-1 Output Top View Power Table 8: RS-485 Port 2 Pinout (P6)
Connect Tech FreeForm/PCI-104 User Manual GPIO Header (P7) When in differential mode, the GPIO header positive (P) and negative (N) signals are adjacent on a standard ribbon cable. Note that the GPIO voltage level is set via hardware. FCG001: L12 populated, enabling 2.5V I/O, including LVDS FCG002: L13 populated, enabling 3.3V I/O...
VIO (connect to 5V) Power It is recommended that a Connect Tech Inc. FreeForm/PCI-104 power supply is used for providing external power. Orientation of the power supply connector is important. Ensure that the clip on the cable aligns with the catch on P8, as shown below.
Connect Tech FreeForm/PCI-104 User Manual Connector’s Mating Components and Cables The following table lists the manufacturer and part number for connectors on the FreeForm/PCI-104, as well as potential mating components. Table 11: Connector Mate Listing Connector Component on Mating components...
Each FreeForm/PCI-104 ships with a FPGA heat sink (27 mm x 27 mm); to be installed by the user. Simply peel of the sticker backing and press firmly onto the FPGA, using proper ESD precautions. If the heat sink size is not suitable for your application, please contact Connect Tech Inc. WARNING In many applications, including high speed memory operations, the FPGA dissipates a significant amount of power.
The reference design and example programs help users quickly develop custom hardware and software applications. Refer to the CD for installation instructions. The latest reference design is always available from: http://devel.connecttech.com/ If a username and password have not already been provided, please contact Connect Tech Support via email support@connecttech.com. Revision 0.02...
Connect Tech FreeForm/PCI-104 User Manual FPGA Configuration The Virtex-5 FPGA can be configured via two methods: JTAG programming chain, using SPI Flash, read on, power-up by FPGA The configuration flash can be programmed (loaded) through three methods: JTAG programming chain (through FPGA), using...
PLLs, and high speed gigabit transceivers. The drawback of these on-chip features is that they consume a lot of power and hence dissipate a lot of heat. As a result Connect Tech, is recommending the installation of a heatsink, included with the product (see section Heat Sink Installation).
Connect Tech FreeForm/PCI-104 User Manual Appendix A: iMPACT Instructions for FPGA Configuration To configure the FPGA via JTAG, connect the JTAG programming cable to ensuring that all JTAG signals align correctly. It is important to note that also has the TRST signal on pin 1, which is not part of Xilinx’s Parallel or USB programming cables.
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Connect Tech FreeForm/PCI-104 User Manual 3) A prompt will ask for a new configuration file. Select the bitstream from the project directory. 4) A prompt will ask for a BSDL file for device number 2 (PLX PCI9056). Click Yes. 5) Browse to the bsdl folder and select PCI9056BA.bsd...
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Connect Tech FreeForm/PCI-104 User Manual 6) iMPACT will add the device to the JTAG chain. 7) Again, a prompt will ask for device number three (National PHY). Browse to the bsdl folder and select DP83849IVS.bsd. The device will be added to the JTAG chain.
Connect Tech FreeForm/PCI-104 User Manual Programming the FPGA 1) Right click on device number one (Virtex-5 FPGA), and select program. The following diagram will appear. Note that verification will only work if an msk file has been created. 2) Select OK to begin programming. After programming is complete, the status window will report:...
Connect Tech FreeForm/PCI-104 User Manual Generating a PROM (MCS) File 1) Double click Prom File Formatter in the Flows window. 2) The “Prepare PROM Files” dialog will appear. Ensure that the following settings are selected: Party SPI PROM MSC PROM File Format 3) Give the file a name, and click Next.
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Connect Tech FreeForm/PCI-104 User Manual 4) Select the PROM density (16M) click Next click Finish. 5) A prompt will ask to add device to data stream 0. Click OK. Select the bitstream from the project directory. Revision 0.02...
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Connect Tech FreeForm/PCI-104 User Manual 6) Click “No” when asked if another device is to be added. Click “OK” to accept the setup. 7) Double Click “Generate File” from the “iMPACT” processes menu. The status will be reported in the console.
Connect Tech FreeForm/PCI-104 User Manual Configuring the FPGA with the SPI Flash In previous Xilinx FPGA configurations, the SPI flash required programming via 3 party JTAG test software or through in-system methods. The following features are new to ISE 9.1/9.2, and are only available on select FPGAs, including the Virtex-5.
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Connect Tech FreeForm/PCI-104 User Manual 3) Browse to the directory containing the previously generated MCS file. Select and click “Open”. 4) The “FPGA SPI Flash Association” window will appear; select “M25P16” (this is the flash device connected to the FPGA).
Connect Tech FreeForm/PCI-104 User Manual Programming the Flash 1) Right click the previously associated flash device, and select program. 2) The programming dialog will appear. Select “Verify” and “Erase Before Programming”, then click “OK.” Revision 0.02...
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Connect Tech FreeForm/PCI-104 User Manual 3) Observe the results in the transcript window. The SPI core is first download to the FPGA device The IDCODE is checked and verified Flash is erased Flash is programmed After completion of the flash programming, the FPGA will attempt to configure itself from the flash.
Connect Tech FreeForm/PCI-104 User Manual Appendix C: Hardware Changes from Revision B This appendix lists the changes between hardware revision B and hardware revision C. The following is a summary of changes: PCB requires only 5V over PCI-104; it previously required 3.3V and 5V A dedicated local bus oscillator was added to generate 50Mhz.
Connect Tech FreeForm/PCI-104 User Manual Reference Design The top level reference design contains a generic parameter which will correctly configure the FPGA for Revision B or Revision C. A separate constraint file UCF is created for Revision B and Revision C, which need to be added to the ISE project manually.
Connect Tech FreeForm/PCI-104 User Manual Hardware Description Connector Pinouts High-speed Serial (P4) The sideband LVCMOS signals (HSS) have been rearranged so that when two FreeForm units are connected: HSS_USER_IO(0) maps to HSS_USER_IO(2) HSS_USER_IO(1) maps to HSS_USER_IO(3) Also, 3.3V pins replace the GND pins; this is because the connector has embedded GND blades.
Connect Tech FreeForm/PCI-104 User Manual External Power Connector (P8) The connector no longer enables 3.3V regulation – it is always enabled. Revision B Revision C Signal Signal 3.3 enable (connect to 5V) VIO (connect to 5V) VIO (connect to 5V)
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