85230 Register Bit Cloning; Security Feature; Table 3: Register Bit Cloning - Connect Tech ComSync/104 User Manual

85230 Register Bit Cloning

Various features of the ComSync/104 board are set up when certain register bits of the ESCC are
programmed. This feature is extremely convenient and reduces the redundancy of setup
functions. When certain bits are written to ESCC registers, the card keeps a copy of those bits to
perform the setup of card features. These Register bits are cloned for each channel of the ESCC,
to perform the following functions:
ESCC
Register Bit(s)
Cloned
WR11.2 TRxC pin as an Input or Output
(Reset state is an Input)
WR4.[5,4,3,2] Various SYNC modes which
require the SYNC pin to be an
Input (Reset to Async mode).
WR1.6 Changes functionality of the
/W//REQ pin (Reset state is the
WAIT function).
WR14.2 Changes the functionality of the
/DTR//REQ pin (Reset state is
the DTR function).

Security Feature

Due to the specialized nature of this product, users may wish to "Secure" their software to the
use of the CTI hardware. This is similar to the use of a "Software Security Dongle" (sometimes
attached to a Parallel port of a PC). The function is implemented by CTI engineers (with
customer input) and can be customer specific. It is programmed into the PLD logic component
on the card during manufacturing.
The security feature is enabled by setting I/O (4).2, setting the required security bits (this is
customer specific), and then reading back the result from I/O (5). When finished with the security
feature, the bit at I/O (4).2 is cleared to return to normal operation.
When the security feature is enabled the following functions are inhibited:
•
Master Interrupt Enable cannot be changed.
•
WAIT states are disabled (IOCHRDY will not activate on PC/104 bus cycles).
•
WAIT Enable cannot be changed.
•
Line Interface Mode cannot be changed for either channel.
Note: The function which can be programmed is limited in scope and
is NOT as fully featured as one would find on a typical "Security
Dongle", but it is usually sufficiently cryptic to slow down pirates

Table 3: Register Bit Cloning

Function on ESCC Function on Card
Controls the direction of the TRxC(±) pins of the
Line Interface to match the setting of the ESCC.
Controls the direction of the SYNC(±) pins of the
Line Interface to match the setting of the ESCC.
(SYNC is an input when External SYNC is
selected or Async mode is selected. All other
times SYNC is an Output).
When programmed to the WAIT function, and
the WAIT Enable [I/O(7).7] bit is ON, the card
will generate wait states onto the PC/104 Bus
during Data reads or writes (using the IOCHRDY
signal).
USE EXTREME CAUTION WHEN USING
THIS MODE, INFINITE WAIT PERIODS
CAN OCCUR!
When programmed for the REQ function the
ESCC pin becomes the DMA signal DRQn
When programmed to the DTR function, the
DTR(±) signals on the line interface are supplied
by the ESCC (WR5.7) and the DMA signal
DRQn is disabled.
When programmed to the REQ function, the
ESCC pin becomes the DMA signal DRQn, and
the DTR(±) line interface signals are provided by
the I/O(4).0,1 bits.
.