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Award BIOS Setup
3.6 Advanced Chipset Features
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional ISA
bus and the PCI bus. It must be stated that these items should never need
to be altered.
provide the best operating conditions for your system. The only time you
might consider making any changes would be if you discovered that data
was being lost while using your system.
CMOS Setup Utility – Copyright © 1984 – 2001 Award Software
System BIOS Cacheable
Video RAM Cacheable
Memory Hole At 15M-16M
AGP Aperture Size (MB)
AGP ISA Aliasing
AGP Fast Write
AGP Data Transfer Mode
AGP Always Compensate
AGP Secondary Lat Timer
SDRAM ECC Setting
Super Bypass Mode
Post Memory Write Enabled
DDR SDRAM Timing by
X Idle Cycle Limit
X Page Hit Limit
X Trc Cycle
X Trp Cycle
X Tras Cycle
X CAS Latency Cycle
X Trcd Cycle
Move
Enter: Select
Help
F5: Previous Values
System BIOS Cacheable:
Selecting "Enabled" allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
The choice: Enabled, Disabled.
The default settings have been chosen because they
Advanced Chipset Features
Disabled
Disabled
Disabled
128
Enabled
Enabled
4X
Enabled
20h
Disabled
Enabled
Disabled
Auto
8 Cycle
8 Cycle
8 Cycle
3 Cycle
7 Cycle
2 Cycle
3 Cycle
+/-/PU/PD: Value
F6: Fail-safe defaults
____________________________
Menu Level
F10: Save
F7: Optimized Defaults
40
Item Help
ESC: Exit
F1: General
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