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JVC RX-DV5RSL Service Manual page 40

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RX-DV5RSL
MN102L62GLF (IC401) : Unit CPU
Pin function
Symbol
I/O
Pin No.
1
WAIT
2
RE
3
SPMUTE
4
WEN
5
LMMUTE
6
CS1
7
CS2
8
HDTYPE
9
DRVMUTE
10
SBRK
11
LSIRST
12
WORD
13
A0
14
A1
15
A2
16
A3
17
VDD
18
SYSCLK
19
VSS
20
XI
21
XO
22
VDD
23
OSCI
24
OSCO
25
MODE
26
A4
27
A5
28
A6
29
A7
30
A8
31
A9
32
A10
33
A11
34
VDD
35
A12
36
A13
37
A14
38
A15
39
A16
40
A17
41
A18
42
A19
43
VSS
44
A20
45
DISCSTP
46
HUGUP
47
TCLOSE
48
WOBBLEF1L
49
HFMON
50
TRVSW
1-40
Function
Micon wait signal input
I
Read enable
O
Spindle muting output to IC251
O
Write enable
O
Non connect
-
Chip select for SODC
O
Non connect
-
HD Type selection
O
Driver mute
O
Short brake terminal
O
LSI reset
O
Bus selection input
I
Address bus 0 for CPU
O
Address bus 1 for CPU
O
Address bus 2 for CPU
O
Address bus 3 for CPU
O
Power supply
-
Non connect
-
Ground
-
Not use (Connect to vss)
-
Non connect
-
Power supply
-
Clock signal input(13.5MHz)
I
Clock signal output(13.5MHz)
O
CPU Mode selection input
I
Address bus 4 for CPU
O
O
Address bus 5 for CPU
Address bus 6 for CPU
O
Address bus 7 for CPU
O
Address bus 8 for CPU
O
Address bus 9 for CPU
O
Address bus 10 for CPU
O
Address bus 11 for CPU
O
Power supply
-
Address bus 12 for CPU
O
Address bus 13 for CPU
O
Address bus 14 for CPU
O
Address bus 15 for CPU
O
Address bus 16 for CPU
O
Address bus 17 for CPU
O
Non connect
-
Non connect
-
Ground
-
Non connect
-
Mechanism state signal output
O
Connect to pick-up
O
Non connect
-
HFM Control output to Q103
O
Detection switch of traverse
I
inside
Symbol
I/O
Pin No.
-
51
SWUPDN
-
52
MECHA_H/V
53
DISCSET
I
-
54
VDD
55
FEPEN
O
O
56
SLEEP
-
57
BUSY
58
REQ
O
-
59
-
60
-
-
-
61
VSS
O
62
EPCS
63
EPSK
O
I
64
EPDI
65
EPDO
O
-
66
VDD
O
67
SCLKO
S2UDT
I
68
O
69
U2SDT
70
CPSCK
O
I
71
P74/SBI1
O
72
SDOUT
-
I
73
I
74
-
75
NMI
I
I
76
ADSCIRQ
I
77
ODCIRQ
I
78
DECIRQ
I
79
CSSIRQ
80
ODCIRQ2
I
I
81
ADSEP
I
82
RST
-
83
VDD
I
84
TEST1
85
TEST2
I
I
86
TEST3
I
87
TEST4
I
88
TEST5
I
89
TEST6
90
TEST7
I
I
91
TEST8
92
VSS
-
I/O
93
D0
I/O
94
D1
95
D2
I/O
I/O
96
D3
97
D4
I/O
I/O
98
D5
I/O
99
D6
100
D7
I/O
Function
Non connect
Connect to ground
Mechanism state signal input
Power supply
Serial enable signal for FEP
Standby signal for FEP
Non connect
Communication request
Connect to TP405
Non connect
Ground
EEPROM chip select
EEPROM clock
EEPROM data input
EEPROM data output
Power supply
Communication clock
Communication input data
Communication output data
Clock for ADSC serial
Not use (Pull down)
ADSC serial data output
Not use (Pull up)
Not use (Pull up)
NMI Terminal
Interrupt input of ADSC
Interrupt input of ODC
Interrupt input of ZIVA
Not use (Pull down)
Interruption of system control
Address data selection input
Reset input
Power supply
Test signal 1 input
Test signal 2 input
Test signal 3 input
Test signal 4 input
Test signal 5 input
Test signal 6 input
Test signal 7 input
Test signal 8 input
Ground
Data bus 0 of CPU
Data bus 1 of CPU
Data bus 2 of CPU
Data bus 3 of CPU
Data bus 4 of CPU
Data bus 5 of CPU
Data bus 6 of CPU
Data bus 7 of CPU

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