Advertisement
RX-DV5RSL
3. Block diagram
CLK
Clock
buffer
CKE
CS
Command
buffer
RAS
CAS
WE
A10
A0
Address
buffer
A9
BS0
BS1
Refresh
counter
1-38
Control
signal
generator
Mode
register
Column
counter
NOTE:
The cell array configuration is 2048 * 256 * 32
Column decoder
Cell array
bank #0
Sense amplifier
Data control
circuit
Column decoder
Cell array
bank #2
Sense amplifier
Column decoder
Cell array
bank #1
Sense amplifier
DQ1
DQ
buffer
DQ31
DQM0~3
Column decoder
Cell array
bank #3
Sense amplifier
Advertisement
