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RX-DV5RSL
W986432DH-7 (IC505) : 32 Bits SDRAM
1.Pin layout
2.Pin function
I/O
Pin No.
-
1
I/O
2
I/O
3
I/O
4~5
I/O
6
I/O
7~8
I/O
9
I/O
10~11
I/O
12
I/O
13
-
14
-
15
I/O
16
-
17
-
18
-
19
-
20
-
21
-
22~23
-
-
24~27
I/O
28
-
29
-
30
I/O
31
I/O
32
I/O
33~34
I/O
35
1-36
Symbol
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Vcc
Multiplexed pins for data out put and input.
DQ0
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
VccQ
Multiplexed pins for data out put and input.
DQ1~DQ2
Separated power from VSS, to improve DQ noise immunity.
VssQ
Multiplexed pins for data out put and input.
DQ3~DQ4
Separated power from VCC, to improve DQ noise immunity.
VccQ
Multiplexed pins for data out put and input.
DQ5~DQ6
Separated power from VSS, to improve DQ noise immunity.
VssQ
Multiplexed pins for data out put and input.
DQ7
No connection
NC
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Vcc
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
DQM0
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Referred to RAS
WE
Referred to RAS
CAS
Command input. When sampled at the rising edge of the clock RAS,
RAS
CAS and WE define the operation to be executed.
Disable or enable the command decoder. When command decoder is
CS
disabled, new command is ignored and previous operation continues.
No connection
NC
Select bank to activate dining row address latch time,
BS0
or bank to read / write during address latch time.
BS1
Multiplexed pins for row and column address. Row address: Ao-A10.
A0~A10
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
DQM2
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Vcc
No connection
NC
Multiplexed pins for data out put and input.
DQ16
Separated power from VSS, to improve DQ noise immunity.
VssQ
Multiplexed pins for data out put and input.
DQ17~18
Separated power from VCC, to improve DQ noise immunity.
VssQ
Function
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