JVC RX-DV5RSL Service Manual page 30

RX-DV5RSL
3.Pin function
Pin No. Symbol I/O
108 VDDDAC
109 VSSDAC
110 DAC3
111 IOM
112 DAC2
113 VAA3
114 DAC1
115 VSSA
116 VREF
117 NC
118 DAC0
119 RSET
120 COMP
121 VSS
122 VIOCLK I/O
123 VSYNC I/O
124 HSYNC I/O
125 VDDIO
126-131 VIO I/O
132 VSSIO
133, 134 VIO I/O
135 VDD
136-139 AD I/O
140 VDDIO
141-144 AD I/O
145 PWE I/O
146 AD I/O
147 VSSIO
148-153 AD I/O
154 VDDIO
155 AD I/O
156 PWE I/O
157, 158 AD I/O
159 VDD
160 SCLK
161 ACK I/O
162 VSSIO
163-168 AD I/O
169 VDDIO
170 PWE I/O
171 VSS
172-176 AD I/O
177 VSSIO
178-180 AD I/O
181 VDDIO
182 PWE I/O
183 ALE I/O
184-187 LA I/O
188 VSSIO
189 RD I/O
190 LHLDA
191 LHLD
192 VDD
193 PCS0
195 XIO I/O
196 VDDIO
197-200 XIO I/O
1-30
DAC digital power
DAC digital ground
O Video DAC3 output
O Cascaded DAC differential output used to dump current into external resistor for power
O Video DAC2 output
DAC analog power
O Video DAC1 output
DAC analog ground
I Input voltage reference for output DACs
Unused
O Video DAC output
O Current setting resistor of output DACs
O Compensation capacitor connection
Core and Ring ground
VCLK input/output for video I/O port function
Bi-directional VSYNC signal for devices
Bi-directional HSYNC signal for devices
I/O pad power =3.3V
Bi-directional digital video port data bus
I/O pad ground
Bi-directional digital video port data bus
Core power =1.8V
Multipleced address/data bus
I/O pad power =3.3V
Multipleced address/data bus
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Multipleced address/data bus
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Multipleced address/data bus
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Multipleced address/data bus
Core power =1.8V
O Ecternal bus clock used for programmable host bus peripherals
Programmable WAIT-/ACK-/RDY- control
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Core and Ring ground
Multipleced address/data bus
I/O pad ground
Multipleced address/data bus
I/O pad power =3.3V
Byte write enable for FLASH, EEPROM, SRAM or peripherals
Address latch enable
Latched address
I/O pad ground
Read
O Bus hold acknwledge in slave mode
I Bus hold request from extrnal master in slave mode
Core power =1.8V
O Peripheral chip select 0
External input/output
I/O pad power =3.3V
External input/output
Function
(3/4)