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Symbol
I/O
Pin No.
I/O
36~37
DQ19~20
I/O
38
VssQ
I/O
39~40
DQ21~22
-
41
VccQ
I/O
DQ23
42
-
Vcc
43
-
Vss
44
I/O
DQ24
45
I/O
VssQ
46
I/O
DQ25~26
47~48
-
49
VccQ
I/O
50~51
DQ27~28
I/O
52
VssQ
I/O
53~54
DQ29~30
-
VccQ
55
I/O
DQ31
56
-
NC
57
-
Vss
58
I/O
DQM3
59
-
60~66
A3~A9
-
CKE
67
I
CLK
68
-
NC
69~70
I/O
DQM1
71
-
72
Vss
I/O
73
NC
I/O
DQ8
74
I/O
VccQ
75
I/O
DQ9~10
76~77
I/O
VssQ
78
I/O
DQ11~12
79~80
I/O
VccQ
81
I/O
DQ13~14
82~83
I/O
84
VssQ
I/O
85
DQ15
-
86
Vss
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Ground for input buffers and logic circuit inside DRAM.
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
No connection
Ground for input buffers and logic circuit inside DRAM.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Multiplexed pins for row and column address. Row address: Ao-A10.
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down rising edge of clock.
System clock used to sample inputs on the rising edge of clock.
No connection
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Ground for input buffers and logic circuit inside DRAM.
No connection
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Ground for input buffers and logic circuit inside DRAM.
Function
RX-DV5RSL
W986432DH-7
1-37
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