Agilent Technologies HP 8719D Service Manual page 342

A11 Phase Lock: Comparing Phase and Frequency
The 10 MHz 1st IF signal from the A64 sampler is fed back to the All phase
lock assembly. In All it is amplified, limited, and filtered to produce a 10 MHz
square wave. This is divided down to 1 MHz, then applied to a phase/frequency
detector that compares it to a crystal controlled 1 MHz signal (PL REF) from
the Al2 reference assembly (see "Al2 Reference: the Crystal Reference
Frequencies," below). Any phase or frequency difference between these two
signals produces a proportional DC voltage.
Tuning the YIG Oscillator
The output of the phase/frequency detector is filtered to remove any 1 MHz
feedthrough, and fed to an integrator. The output of the integrator is converted
to a tune current. This brings the appropriate YIG oscillator closer to the
desired frequency, which in turn reduces the phase/frequency detector output
voltage. When the voltage is reduced to zero, and the divided-down 1st IF
frequency is equal to the 1 MHz reference frequency PL REF, phase lock is
achieved.
Phase Locked Sweep
When the source is phase locked to the synthesizer at the start frequency, the
synthesizer starts to sweep. The phase-locked loop forces the source to track
the synthesizer, maintaining a constant 10 MHz 1st IF signal.
The full sweep is generated in a series of subsweeps, by phase locking the
source signal to the harmonic multiples of the synthesizer. At the transitions
between subsweeps, phase lock is broken, the source is held at this frequency.
Theory of Operation