Renesas RTE7702500EAB00000J User Manual page 19

Emulation Adapter
(12) Jumper block: JP9 (FLMD1)
JP9 (FLMD1)
Open-circuit
1-2 short-circuit
2-3 short-circuit
(default)
(13) Jumper block: JP13 (FLMD1_SEL)
JP13 (FLMD1_SEL)
Open-circuit
1-2 short-circuit
(default)
2-3 short-circuit
(14) Jumper block: JP15 (RES_SEL)
JP15 (RES_SEL)
Open-circuit
1-2 short-circuit
(default)
2-3 short-circuit
(15) Jumper block: JP1 (VDD_EMU)
JP1 (VDD_EMU)
Open-circuit
Short-circuit
(default)
(16) Jumper block: JP4 (EMUVDD)
JP4 (EMUVDD)
Open-circuit
1-2 short-circuit
(default)
2-3 short-circuit
R20UT5180EJ0110 Rev. 1.10
Sep.12.22
Setting prohibited.
The FLMD1 pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
The FLMD1 pin for the debug chip is controlled by the target system.
Setting prohibited.
The FLMD1 pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
Setting prohibited.
Setting prohibited.
The RESET pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
Setting prohibited.
When the SYSVCC power for the debug chip is 2.5 V or more, the VDD power or
EMUVDD power is generated from the emulation adapter.
When the PWRCTL pin for the debug chip is high, the VDD power or EMUVDD
power is generated from the emulation adapter.
When the PWRCTL pin for the debug chip is in the high-impedance state and the
SYSVCC power is 2.5 V or more, the VDD power or EMUVDD power is generated
from the emulation adapter.
Setting prohibited.
When the PWRCTL pin for the debug chip is high or the SYSVCC power is 2.5
V or more, the EMUVDD power is generated from the emulation adapter.
This specification depends on the settings of JP1.
The EMUVDD power is always generated from the emulation adapter.
Names and Functions of Hardware
Specification
Specification
Specification
Specification
Specification
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