Xilinx Alveo X3522 User Manual page 7

Table 2: Terms and Definitions (cont'd)
Term
ECC
EFCT
FCS
FEC
FPGA
IRQ
LAN
MCDI
MTU
NC-SI
NIC
NUMA
Onload
PCIe
PF
RS-FEC
RSS
RX, Rx
SECDED
SFP
SMBus
TSO
TX, Tx
UEFI
UUID
UG1523 (v1.0) October 18, 2022
Alveo X3522 User Guide
Error Correction Code.
The native interface for an X3522.
Frame Check Sequence.
Error-detecting code added to an Ethernet frame.
Forward Error Correction.
Employs redundancy in channel coding as a technique used to reduce bit errors.
Field Programmable Gate Array.
A semiconductor device that is based around a matrix of configurable logic blocks
connected via programmable interconnects.
Interrupt Request.
Local Area Network.
Management CPU Driver Interface.
Passes messages and events between the host driver and the X3522 firmware.
Maximum Transmission Unit.
The maximum packet size that can be transmitted.
Network Controller Sideband Interface.
An electrical interface and protocol for out-of-band system management.
Network Interface Controller.
Non-Uniform Memory Access.
A multiprocessing design where memory is local to clusters of processors.
A high performance user-level network stack from Xilinx, which accelerates TCP and UDP
network I/O.
Peripheral Component Interconnect Express.
A high-speed serial bus used to connect components.
Physical Function.
A PCIe physical device.
A type of Forward Error Correction also known as Reed Solomon.
Receive Side Scaling.
Enables packet receive-processing to scale with the number of available CPU cores.
Receive.
Single Error Correction / Double Error Detection.
Error processing that can correct a 1-bit error, and detect a 2-bit error.
Small Form-factor Pluggable.
A single-channel network transceiver design.
System Management Bus.
A single-ended two-wire bus for lightweight communication between system components.
TCP Segmentation Offload.
Offloads the splitting of outgoing TCP data into packets to the adapter.
Transmit.
Unified Extensible Firmware Interface.
Provides support for disk-less booting to a target operating system.
Universally Unique Identifier.
A 128-bit identifier that is unique and persistent.
Chapter 1: Introduction
Definition
Send Feedback
www.xilinx.com
7