Xilinx Alveo X3522 User Manual page 26

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In this example there are four receive queues per interface, for a total of 16 receive queues.
2. Identify the current receive ring buffer size for each interface (in packet buffers):
$ ethtool -g <interface>
For example:
$ ethtool -g enp1s0f0np0
Ring parameters for enp1s0f0np0:
Pre-set maximums:
RX:
RX Mini:
RX Jumbo:
TX:
Current hardware settings:
RX:
RX Mini:
RX Jumbo:
TX:
In this example, the receive ring buffer size is 2048 packet buffers.
3. Calculate the minimum number of huge pages that are required:
• Each receive queue requires the following minimum number of huge pages:
ROUNDUP (rx_ring_buffer_size ÷ 1024) + 1
• Assuming the receive ring buffer size is the same for all interfaces, you can use the
following formula:
<num_rx_queues> × (ROUNDUP (rx_ring_buffer_size ÷ 1024) + 1)
So for this example, you would require a minimum of:
16 × (ROUNDUP (2048 ÷ 1024) + 1)
which is 48 huge pages.
You might later increase this value when tuning your application for best performance.
UG1523 (v1.0) October 18, 2022
Alveo X3522 User Guide
enp1s0f0np0-rx-3
2183 0
enp1s0f0np2-rx-3
1113 0
enp1s0f1np1-rx-0
1233 561
enp1s0f1np3-rx-0
342 1209
enp1s0f1np1-rx-1
560 367
enp1s0f1np3-rx-1
0 0
enp1s0f1np1-rx-2
342 0
enp1s0f1np3-rx-2
921 1000
enp1s0f1np1-rx-3
343 400
enp1s0f1np3-rx-3
6144
0
0
512
2048
0
0
512
2 47 PCI-MSI 524323-
40 1081 PCI-MSI 526336-
0 440 PCI-MSI 526368-
681 0 PCI-MSI 526337-
883 422 PCI-MSI 526369-
1151 1081 PCI-MSI 526338-
408 1482 PCI-MSI 526370-
142 169 PCI-MSI 526339-
0 1489 PCI-MSI 526371-
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Chapter 5: Tuning
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