Xilinx Alveo X3522 User Manual page 31

• To view the interrupts that are currently in use, and determine the queues for which they are
being used:
$ cat /proc/interrupts
Note: The example outputs for this command show only the interrupts for a single X3522 interface, and
omit all output related to other devices.
Initially, you see the interrupts for the receive queues (<interface>-rx-<queue_num>)
and for the default transmit queue (<interface>-tx-0):
$ cat /proc/interrupts
CPU0
...
114:
PCI-MSI 49283072-edge
116: 125010
PCI-MSI 49283073-edge
118: 58288
PCI-MSI 49283074-edge
120: 125010
PCI-MSI 49283075-edge
122:
PCI-MSI 49283076-edge
124:
PCI-MSI 49283077-edge
126:
PCI-MSI 49283078-edge
128:
PCI-MSI 49283079-edge
130:
PCI-MSI 49283080-edge
...
As applications start, the interrupts for their transmit queues are added to the output (onld-
<n> below):
$ cat /proc/interrupts
CPU0
...
114:
PCI-MSI 49283072-edge
116: 125010
PCI-MSI 49283073-edge
118: 58288
PCI-MSI 49283074-edge
120: 125010
PCI-MSI 49283075-edge
122:
PCI-MSI 49283076-edge
124:
PCI-MSI 49283077-edge
126:
PCI-MSI 49283078-edge
128:
PCI-MSI 49283079-edge
130:
PCI-MSI 49283080-edge
132:
PCI-MSI 49283081-edge
133:
UG1523 (v1.0) October 18, 2022
Alveo X3522 User Guide
CPU1 CPU2
44 0 0
enp1s0f0np0-rx-0
0 0
enp1s0f0np0-rx-1
44 1
enp1s0f0np0-rx-2
0 0
enp1s0f0np0-rx-3
0 0 0
enp1s0f0np0-rx-4
0 0 0
enp1s0f0np0-rx-5
0 0 0
enp1s0f0np0-rx-6
0 0 0
enp1s0f0np0-rx-7
18 0 1
enp1s0f0np0-tx-0
CPU1 CPU2
44 0 0
enp1s0f0np0-rx-0
0 0
enp1s0f0np0-rx-1
44 1
enp1s0f0np0-rx-2
0 0
enp1s0f0np0-rx-3
0 0 0
enp1s0f0np0-rx-4
0 0 0
enp1s0f0np0-rx-5
0 0 0
enp1s0f0np0-rx-6
0 0 0
enp1s0f0np0-rx-7
18 0 1
enp1s0f0np0-tx-00
0 0 0
onld-0
0 0 0
CPU3 CPU4 CPU5
0 1
0 1
0 0
0 1
0 0
0 0
0 0
0 0
0 0
CPU3 CPU4 CPU5
0 1
0 1
0 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
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Chapter 5: Tuning
CPU6 CPU7
0 125010 0
0 44 0
0 66723 0
0 0 44
0 0 0
0 0 0
0 0 0
0 0 0
0 31 0
CPU6 CPU7
0 125010 0
0 44 0
0 66723 0
0 0 44
0 0 0
0 0 0
0 0 0
0 0 0
0 31 0
0 0 0
0 0 0
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