SOLTEK SL-65EB User Manual page 44

65EB
Video BIOS Cacheable Choose Enabled or Disabled. When enabled, the
Video RAM Cacheable Choose Enabled or Disabled. When enabled, the
8/16 bit I/O Recovery
Memory Hole At 15M-
Rassive Release When Enabled, CPU to PCI bus accesses are allow
Delayed Transaction The chipset has an embedded 32-bit posted write
AGP Aperture Size Choose 4, 8, 16, 32, 64, 128 or 256 MB. Memory
3. Press <ESC> to return to the Main Menu when you finish setting up all
items.
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access to the VGA RAM addressed is cached.
access to the VGA RAM addressed is cached.
The I/O recovery mechanism adds bus clock cycles
Time between PCI-originated I/O cycles to the ISA bus. This
delay takes place because the PCI bus is much faster
than the ISA bus.
You can reserve this area of system memory for ISA
16M adapter ROM. When this area is reserved, it can not
be cached. The user information of peripherals that
need to use this area of system memory usually dis-
cusses their memory requirements.
during passive release. Otherwise, the arbiter only
accepts another PCI master access to local DRAM.
buffer to support delay transactions cycles. Select
Enabled to support compliance with PCI specifica-
tion version 2.1.
mapped and graphics data structures can reside in a
Graphics Aperture. This area is like a linear buffer.
BIOS will automatically report the starting address of
this buffer to the O.S.