SOLTEK SL-65EB User Manual page 43

EDO RASx# Wait State The board designer may elect to insert one additional
SDRAM RAS-to-CAS
SDRAM RAS
Precharge Time
SDRAM CAS latency
SDRAM Precharge
DRAM Data integrity
System BIOS
Cacheable
wait state before RASx# is asserted for row misses,
thus allowing one additional MAX [13:0] setup time to
RASx# assertion. This field applies only if EDO DRAM
is installed in the system.
This field lets you insert a timing delay between the
Delay CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed. Fast gives faster
performance; and Slow gives more stable
performance. This field applies only when synchro-
nous DRAM is installed in the system.
If an insufficient number of cycles is allowed for the
RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may
fail to retain data. Fast gives faster performance; and
Slow gives more stable performance. This field ap-
plies only when synchronous DRAM is installed in
the system.
When synchronous DRAM is installed, the number of
Time clock cycles of CAS latency depends on he DRAM
timing. Do not reset this field from the default value
specified by the system designer.
When Enabled, all CPU cycles to SDUAM result in
Control an All Banks Precharge Command on the SDRAM
interface.
Select Parity or ECC (error-correcting code), accord-
Mode ing to the type of installed DRAM.
Choose Enabled or Disabled. When enabled, the
access to the system BIOS ROM addressed at
F0000H - FFFFFH is cached.
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