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4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
4.11.1 Configuration of serial interface
The S1C63454 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 4.11.1.1.
The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of three
types of master mode (internal clock mode: when the S1C63454 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C63454 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY signal which indicates whether or not the
serial interface is available to transmit or receive can be output to the SRDY terminal.
SIN
(P10)
SCLK
or
SCLK
(P12)
The input/output ports of the serial interface are shared with the I/O ports P10–P13, and function of
these ports can be selected through the software.
P10–P13 terminals and serial input/output correspondence are as follows:
Master mode
P10 = SIN (I)
P11 = SOUT (O)
P12 = SCLK (O)
P13 = I/O port (I/O)
Note: At initial reset, P10–P13 are set to I/O ports.
When using the serial interface, switch the function (ESIF = "1") in the initial routine.
S1C63454 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SD0–SD7
Shift register (8 bits)
SCPS
SCS0 SCS1
Serial clock
selector
f
OSC1
Serial clock
generator
Programmable
timer 1 underflow
signal
Serial I/F
activating
circuit
SCTRG
Fig. 4.11.1.1 Configuration of serial interface
Slave mode
P10 = SIN (I)
P11 = SOUT (O)
P12 = SCLK (I)
P13 = SRDY (O)
EPSON
Output
latch
Serial clock
Serial I/F interrupt
counter
control circuit
SOUT
(P11)
Interrupt
request
SRDY
or
SRDY
(P13)
69
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