Epson S1C63454 Technical Manual page 104

CHAPTER 5: SUMMARY OF NOTES
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when f is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
OSC1
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of
the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to the
PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is decremented
(-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually stops.
Figure 5.2.1 shows the timing chart for the RUN/STOP control.
Input clock
PTRUN0/PTRUN1 (RD)
PTRUN0/PTRUN1 (WR)
PTD0X/PTD1X
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned ON and OFF by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(5) The counter mode selection register EVCNT should be set to "0" when timer 0 is used as a down
counter. Otherwise it will cause malfunction.
Serial interface
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is halted
(i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
Sound generator
(1) Since it generates a BZ signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes ON/OFF due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is OFF (BZE = "0") and will be
invalid when the normal buzzer output is ON (BZE = "1").
(3) The buzzer signal is generated by dividing the OSC1 oscillation clock. Since the frequencies and times
that are described in this section are the values in the case of crystal oscillation (32.768 kHz, Typ.),
they differ when CR oscillation (60 kHz, Typ.) is selected.
94
"1" (RUN)
writing
42H
Fig. 5.2.1 Timing chart for RUN/STOP control
EPSON
"0" (STOP)
writing
41H 40H 3FH 3EH 3DH
S1C63454 TECHNICAL MANUAL