Osc3 Oscillation Circuit - Epson S1C63454 Technical Manual

4.3.3 OSC3 oscillation circuit

The S1C63454 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro-
grammable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscilla-
tion circuit. When CR oscillation is selected, only a resistance is required as an external element. When
ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are
required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C
GC
C
DC
V
SS
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
R between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
CR2
Characteristics" for resistance value of R
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor C
and OSC4 terminals, and capacitor C
connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
S1C63454 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
C
CR
OSC3
OSC4
(a) CR oscillation circuit
OSC3
OSC4
(b) Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
.
CR2
between the OSC4 and V
DC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
R
DC
terminals. For both C
SS
EPSON
between the OSC3
GC
and C ,
GC DC
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