Precautions On Mounting; Oscillation Circuit - Epson S1V3G340 Hardware Specification

9.6
S1V3G340 Hardware Specification
(Rev. 1.0)
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Precautions on Mounting

The following shows the precautions when designing the board and mounting the IC.
9.6.1

Oscillation Circuit

Oscillation characteristics change depending on conditions such as components used
(oscillator, Rf, Rd, Cg, Cd) and board pattern. In particular, when a ceramic or crystal
oscillator is used, evaluate the components adequately under real operating conditions by
mounting them on the board before the external resistor (Rf, Rd) and capacitor (Cg, Cd)
values are finally decided.
Disurbances of the oscillation clock due to noise may cause a malfunction. To prevent this,
the following points should be taken into consideration.
• Components that are connected to the OSCI and OSCO pins, such as oscillator,
resistors and capacitors, should be connected in the shortest line.
• Whenever possible, configure digital signal lines with at least three millimeters
clearance from the OSCI and OSCO and the components and lines connected to these
pins. In particular, signals thet are switched frequently must not be placed near these
pins, components, and lines. The same applies to all layers on the multi-layered board
as the distance between the layers is around 0.1 to 0.2 mm. Furthermore, do not
configure digital signal lines in parallel with these components and lines when
arranging them on the same or another layer of the board. Such an arrangement is
strictly prohibited, even with clearance of three millimeters or more. Also, avoid
arranging digital signal lines across these components and signal lines.
• Shield the OSCI and OSCO pins and lines connected to those pins as well as the
adjacent layers of the board using VSS. As shown in Figure 9.4, shield the wired layers
as much as possible. Whenever possible, make the whole adjacent layers the ground
layers, or ensure there is adequate shielding to a radius of five millimeters around the
above pins and lines. Do not configure digital signal lines in parallel with components
and lines even if such components and lines on other layers.
Figure 9.4 Example of oscillation circuit VSS pattern
OSCI
OSCO
VSS
EPSON
9. Reference Material
37