Table 18 Ultra Dma Cycle Timings (Initiating Read); Figure 9 Ultra Dma Cycle Timing Chart (Initiating Read) - Hitachi CinemaStar P7K500 Specifications

5.2.4 Ultra DMA timings
The Ultra DMA timing meets Mode 0,1,2,3 4, and 5 of the Ultra DMA Protocol.
5.2.4.1
Initiating Read DMA
DMARQ
DMACK-
STOP
HDMARDY-
DSTROBE
DD(15:00)
xxxxxxxxxxxxxxxxxxxxxxxxx
Host drives DD
PARAMETER
DESCRIPTION
(all values in ns)
tUI Unlimited interlock time
Setup time before
tACK
–DMACK
tENV
Envelope time
Minimum time before
tZIORDY
driving IORDY
tFS First DSTROBE time
tCYC Cycle time
t2CYC Two cycle time
Maximum time allowed for
tAZ
output drivers to release
Maximum time allowed for
tZAD
output drivers to assert
tDS Data setup time (at host)
tDH Data hold time (at host)
Time from data output
released-to-driving until
tDZFS
the first transition of critical
timing

Table 18 Ultra DMA cycle timings (Initiating Read)

HITACHI Deskstar & CinemaStar P7K500 Hard Disk Drive specification (Rev 1.1)
tUI
tACK tENV
tACK tENV
tZIORDY
tAZ

Figure 9 Ultra DMA cycle timing chart (Initiating Read)

MODE0 MODE1
MIN MAX MIN MAX
0 – 0
20 – 20
20 70 20
0 – 0
0 230 0 200
112 – 73
230 – 153
– 10 –
0 – 0
15 – 10
5 – 5
70 - 48
t2CYC
tFS tCYC
tDZFS
tDS
tZAD
xxx xxx
RD Data RD Data
Device drives DD
MODE2 MODE3
MIN MAX MIN MAX
– 0 0 0 –
– 20 – 20 –
70 20 70 20 55
– 0 – 0 –
0 170 0 130
– 54 – 39 –
– 115 – 86 –
10 – 10 – 10
– 0 – 0 –
– 7 – 7 –
– 5 – 5 –
- 31 - 20 -
26
tCYC
tDS
tDH tDH
xxx
RD Data
MODE4 MODE5 MODE6
MIN MAX MIN MAX MIN
0 – 0 – 0
20 – 20 – 20
20 55 20 50 20
0 – 0 – 0
0 120 0 90 0
25 – 17 – 13
57 – 38 – 29
– 10 – 10 –
0 – 0 – 0
5 – 4 – 2.6
5 – 4.6 – 3.5
6.7 - 25 - 17.5
MAX
–
–
50
–
80
–
–
10
–
–
–
-