Page 1 Hard Disk Drive Specification Deskstar 7K250 3.5 inch Ultra ATA/100 hard disk drive Models: HDS722525VLAT80 HDS722516VLAT80 HDS722516VLAT20 HDS722512VLAT80 HDS722512VLAT20 HDS722580VLAT20 HDS722540VLAT20 Version 1.5 12 December 2005...
Page 3 Hard Disk Drive Specification Deskstar 7K250 3.5 inch Ultra ATA/100 hard disk drive Models: HDS722525VLAT80 HDS722516VLAT80 HDS722516VLAT20 HDS722512VLAT80 HDS722512VLAT20 HDS722580VLAT20 HDS722540VLAT20 Version 1.5 12 December 2005...
Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your coun- try.
Page 5: Table Of Contents
Table Of Contents 1.0 General........................1 1.1 Introduction....................1 1.2 References....................1 1.3 Abbreviations...................1 1.4 Caution.....................3 2.0 General features of the drive ................5 3.0 Fixed-disk subsystem description..............9 3.1 Control electronics ...................9 3.2 Head disk assembly ................9 3.3 Actuator ....................9 4.0 Drive characteristics ..................11 4.1 Default logical drive parameters..............11 4.2 Data sheet....................12 4.3 Drive organization ...................13...
Page 6 6.3.2 Power supply current (typical)............29 6.3.3 Power supply generated ripple at drive power connector....31 6.4 Reliability....................32 6.4.1 Data integrity ..................32 6.4.2 Cable noise interference..............32 6.4.3 Start/stop cycles ................32 6.4.4 Preventive maintenance ..............32 6.4.5 Data reliability ................32 6.4.6 Required power-off sequence ............32 6.5 Mechanical specifications................33 6.5.1 Physical dimensions and weight .............33 6.5.2 Mounting hole locations ..............34...
Page 7 7.6.2 Read DRQ interval time ..............50 7.7 Multi word DMA timings ................51 7.8 Ultra DMA timings ..................52 7.8.1 Initiating Read DMA ..............52 7.8.2 Host Pausing Read DMA..............53 7.8.3 Host Terminating Read DMA............54 7.8.4 Device Terminating Read DMA.............55 7.8.5 Initiating Write DMA ..............56 7.8.6 Device Pausing Write DMA ............57 7.8.7 Device Terminating Write DMA ............58 7.8.8 Host Terminating Write DMA............59...
Page 8 10.6.2 Power management commands ............78 10.6.3 Standby timer ................78 10.6.4 Interface capability for power modes ...........79 10.7 S.M.A.R.T. Function ................80 10.7.1 Attributes ..................80 10.7.2 Attribute values................80 10.7.3 Attribute thresholds...............80 10.7.4 Threshold exceeded condition ............80 10.7.5 S.M.A.R.T. commands ..............80 10.7.6 Off-line read scanning ..............80 10.7.7 Error log ..................81 10.7.8 Self-test ..................81 10.8 Security Mode Feature Set..............82...
Page 9 12.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)110 12.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h).111 12.2.4 DEVICE CONFIGURATION SET (subcommand C3h) .....111 12.3 Execute Device Diagnostic (90h) ............114 12.4 Flush Cache (E7h) .................115 12.5 Flush Cache Ext (EAh) ................116 12.6 Format Track (50h) ................117 12.7 Format Unit (F7h) ..................118 12.8 Identify Device (ECh)................119 12.9 Idle (E3h/97h) ..................127...
Page 10 12.38.1 Set Max Set Password (Feature=01h).........178 12.38.2 Set Max Lock (Feature=02h)............179 12.38.3 Set Max Unlock (Feature = 03h) ..........180 12.38.4 Set Max Freeze Lock (Feature = 04h) ........181 12.39 Set Max Address Ext (37h)..............182 12.40 Set Multiple (C9h) ................184 12.41 Sleep (E6h/99h) ...................185 12.42 S.M.A.R.T.
Page 11 List of Tables Table 1.Formatted capacities ..................11 Table 2.Mechanical positioning performance ............12 Table 3.Cylinder allocation..................13 Table 4.Command overhead ..................15 Table 5.Mechanical positioning performance ............15 Table 6.Full stroke seek time ..................16 Table 7.Head switch time ..................16 Table 8.Single track seek time ...................17 Table 9.Latency Time ....................17 Table 10.Drive ready time ..................17 Table 11.Data transfer speed ..................18...
Page 12 Table 42.Default Register Values ................74 Table 43.Diagnostic codes ..................74 Table 44.Reset error register values ................75 Table 45.Power conditions ..................79 Table 46.Command table for device lock operation..........86 Table 47.Command Set (1 of 2).................105 Table 48.Command Set (2 of 2).................106 Table 49.Command Set (subcommand)..............107 Table 50.Check Power Mode command (E5h/98h)...........109 Table 51.Check Power Mode Command (E5h/98h)..........110 Table 52.Device Configuration Overlay Features register values ......110...
Page 13 Table 88.Read Native Max Address Ext command (27h) .........153 Table 89.Read Sectors Command (20h/21h) .............154 Table 90.Read Sector(s) Ext command (24h)............156 Table 91.Read Verify Sectors (40h/41h) ..............158 Table 92.Read Verify Sector(s) command (42h)............160 Table 93.Recalibrate (1xh) ..................162 Table 94.Security Disable Password (F6h)..............163 Table 95.Password Information for Security Disable Password command....163 Table 96.Security Disable Password (F3h)..............164 Table 97.Security Erase Unit (F4h) ................165...
Page 14 Table 134.Write Log Ext Command (3Fh)...............210 Table 135.Write Long (32h/33h) ................211 Table 136.Write Multiple (C5h) ................213 Table 137.Write Log Ext Command (3Fh)...............215 Table 138.Write Sectors command (30h/31h) ............217 Table 139.Write Sector(s) Command (34h) .............219...
Page 15: Introduction
1.0 General 1.1 Introduction This document describes the specifications of the Deskstar 7K250, a 3.5-inch hard disk drive with ATA interface and a rotational speed of 7200 RPM. HDS722540VLAT20 41.1GB HDS722580VLAT20 82.3GB HDS722512VLAT20/ 123.5GB HDS722512VLAT80 HDS722516VLAT20/ 164.7GB HDS722516VLA820 HDS722525VLAT80 250GB These specifications are subject to change without notice.
Page 16 field replacement unit gravity (a unit of force) (32 ft/sec) per Hertz 1,000,000,000 bits 1,000,000,000 bytes ground hexadecimal hard disk drive Hertz Input integrated lead suspension Input/Output International Standards Organization 1,000 bytes Kbpi 1000 bits per inch kgf-cm kilogram (force)-centimeter kilohertz logical block addressing unit of A-weighted sound power...
Page 17: Caution
second SELV secondary low voltage S.M.A.R.TSelf-Monitoring, Analysis, and Reporting Technology tracks per inch track transistor-transistor logic Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.4 Caution • Do not apply force to the top cover. • Do not cover the breathing hole on the top cover. •...
Page 18 Deskstar 7K250 Hard Disk Drive Specification...
Page 19: General Features Of The Drive
2.0 General features of the drive • Formatted capacities of 40 GB - 250 GB • Spindle speeds of 7200 RPM • Fluid Dynamic Bearing motor • Enhanced IDE interface • Sector format of 512 bytes/sector • Closed-loop actuator servo •...
Page 20 Deskstar 7K250 Hard Disk Drive Specification...
Page 21 Part 1. Functional specification Deskstar 7K250 Hard Disk Drive specification...
Page 22 Deskstar 7K250 Hard Disk Drive Specification...
Page 23: Control Electronics
3.0 Fixed-disk subsystem description 3.1 Control electronics The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and var- ious drivers and receivers. The control electronics performs the following major functions: • Controls and interprets all interface signals between the host controller and the drive. •...
Page 24 Deskstar 7K250 Hard Disk Drive Specification...
Page 25: Default Logical Drive Parameters
4.0 Drive characteristics 4.1 Default logical drive parameters Table 1: Formatted capacities HDS722540VLAT20 HDS722580VLAT20 HDS722512VLAT20 HDS722512VLAT80 Physical Layout Label capacity (GB) Bytes per sector Sectors per track 567-1170 567-1170 567-1170 Number of heads Number of disks Data sectors per cylinder 567-1170 1134-2340 1701-3510...
Page 26: Data Sheet
Notes: Number of cylinders: For drives with capacities greater than 8.45 GB the Identify Device information word 01 limits the number of cylinders to 16, 383 per the ATA specification. Logical layout: Logical layout is an imaginary drive parameter (that is, the number of heads) which is used to access the drive from the system interface.
Page 27: Drive Organization
4.3 Drive organization 4.3.1 Drive format Upon shipment from manufacturing the drive satisfies the sector continuity in the physical format by means of the defect flagging strategy described in Section 5.0, “Defect flagging strategy” on page 21 in order to provide the maximum performance to users.
Page 28 This cylinder contains the user data which can be sent and retrieved via read/write commands and a spare area for reassigned data. Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect location. Deskstar 7K250 Hard Disk Drive Specification...
Page 29: Performance Characteristics
4.4 Performance characteristics Drive performance is characterized by the following parameters: • Command overhead • Mechanical head positioning Seek time Latency • Data transfer speed • Buffering operation (Look ahead/Write cache) All the above parameters contribute to drive performance. There are other parameters that contribute to the perfor- mance of the actual system.
Page 30: Table 6.Full Stroke Seek Time
The terms “Typical” and “Max” are used throughout this document and are defined as follows: Typical The average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions.
Page 31: Table 8.Single Track Seek Time
4.4.2.4 Cylinder switch time (cylinder skew) Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block after reading the last sector in the current cylinder. The measuring method is given in Section 4.4.5, “Throughput” on page 19. 4.4.2.5 Single track seek time (without command overhead, including settling) Table 8: Single track seek time Function...
Page 32: Table 11.Data Transfer Speed
4.4.4 Data transfer speed Table 11: Data transfer speed Data transfer speed 250GB model (Mbytes/s) Disk-Buffer transfer (Zone 0) Instantaneous - typical 72.1 Sustained - read typical 61.4 Disk-Buffer transfer (Zone 29) Instantaneous - typical 34.9 Sustained - read typical 29.7 Buffer - host (max) •...
Page 33: Throughput
4.4.5 Throughput 4.4.5.1 Simple sequential access The following table illustrates simple sequential access for the three-disk enclosure. Table 12: Simple Sequential Access performance Operation Typical (sec) Max (sec) Sequential Read (Zone 0) 0.32 Sequential Read (Zone 29) 0.61 0.64 The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by 128 read commands.
Page 34: Table 15.Description Of Operating Modes
B = Average seek time (sec) C = Latency D = Average sustained disk-buffer transfer rate (byte/s) E = Buffer-host transfer rate (byte/s) 4.4.6 Operating modes 4.4.6.1 Description of operating modes Table 15: Description of operating modes Operating mode Description Start up time period from spindle stop or power down.
Page 35: Defect Flagging Strategy
5.0 Defect flagging strategy Media defects are remapped to the next available sector during the Format Process in manufacturing. The mapping from LBA to the physical locations is calculated by an internally maintained table. Shipped format • Data areas are optimally used. •...
Page 36 Deskstar 7K250 Hard Disk Drive Specification...
Page 37: Jumper Settings
6.0 Specification 6.1 Jumper settings 6.1.1 Jumper pin location Jum per pins Figure 1: Jumper pin location 6.1.2 Jumper pin identification Pin I Pin A DERA001.prz Pin B Figure 2: Jumper pin identification Deskstar 7K250 Hard Disk Drive Specification...
Page 38: Jumper Pin Assignment
6.1.3 Jumper pin assignment There are four jumper settings as shown in the following sections: • 16 logical head default (normal use) • 15logical head default • 32 GB clip • Power up in standby Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device 1 Slave Present as shown in the following figures.
Page 39: Logical Head Default
Notes: 1. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: • When CSEL is grounded or at a low level, the drive address is 0 (Device 0). •...
Page 40: Table 18.Jumper Positions For Capacity Clip To 2Gb/32Gb
6.1.4.3 Capacity clip to 32GB The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1 (Slave) Present while setting the drive capacity down to 32 GB for the purpose of compatibility. Table 18: Jumper positions for capacity clip to 32GB DEVICE 0 (M aster) DEVICE 1...
Page 41 Notes: 1. These jumper settings are used for limiting power supply current when multiple drives are used. 2. Command to spin up is SET FEATURES (subcommand 07h). Refer to 12.28 Set Features. 3. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL mode the drive address is determined by AT interface signal #28 CSEL as follows: •...
Page 42: Environment
6.2 Environment 6.2.1 Temperature and humidity Table 20: Temperature and humidity Operating conditions Temperature 5C to 55ºC (See note below) Relative humidity 8 to 90%, non-condensing Maximum wet bulb temperature 29.4ºC, non-condensing Maximum temperature gradient 15ºC/hour Altitude –300 to 3,048 m Non-operating conditions Temperature –40C to 65ºC...
Page 43: Corrosion Test
6.2.2 Corrosion test The drive shows no sign of corrosion inside and outside of the hard disk assembly and is functional after being sub- jected to seven days at 50°C with 90% relative humidity. 6.3 DC power requirements Damage to the drive electronics may result if the power supple cable is connected or disconnected to the legacy power connector while power is being applied to the drive (no hot plug/unplug is alloweed).
Page 44 Random seeks at 40% duty cycle Seek duty = 30%, W/R duty = 45%, Idle duty = 25% Power supply current of 120 +5 Volts (mA) +12 Volts (mA) Total (W) GB and 160 GB models Pop mean Pop mean Std dev values in milliamps, RMS Idle average...
Page 45: Table 23.Power Supply Generated Ripple At Drive Power Connector
Power supply current of +5 Volts (mA) +12 Volts (mA) Total (W) 40GB and 80GB models Pop mean Pop mean Std dev values in milliamps, RMS Start up (max) 1700 Standby average Sleep average 6.3.3 Power supply generated ripple at drive power connector Table 23: Power supply generated ripple at drive power connector Maximum (mV pp) +5 V dc...
Page 46: Reliability
6.4 Reliability 6.4.1 Data integrity No more than one sector is lost at Power loss condition during the write operation when the write cache option is disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer data, it is recommended that the last write access before power off be issued after setting the write cache off.
Page 47: Mechanical Specifications
6.5 Mechanical specifications 6.5.1 Physical dimensions and weight 2 5 .4 } 0 .4 1 01 .6 } 0 .4 1 4 6 } 0 .6 B R E A T H E R H O L E (*) D ia . 2 .0 } 0 .1 3 8 .9 } 0 .4...
Page 48: Mounting Hole Locations
B R E A T H E R H O L E Figure 7: Bottom and side of 40GB - 80GB view with breather hole and mounting hole locations 6.5.2 Mounting hole locations The mounting hole locations and size of the drive are shown below. All dimensions are in mm. (6X) Max.
Page 49: Connector Locations
6.5.3 Connector locations Figure 9: Connector locations 6.5.4 Drive mounting The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted. For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting hardware.
Page 50: Table 24.Random Vibration Psd
6.6 Vibration and shock All vibration and shock measurements recorded in this section are made with a drive that has no mounting attach- ments for the systems. The input power for the measurements is applied to the normal drive mounting points. 6.6.1 Operating vibration 6.6.1.1 Random vibration The test is 30 minutes of random vibration using the power spectral density (PSD) levels shown below in each of...
Page 51: Operating Shock
The overall RMS (root mean square) level of vibration is 1.04 G. 6.6.2.2 Swept sine vibration • 2 G (zero-to-peak), 5 to 500 to 5 Hz sine wave • 0.5 oct/min sweep rate • 3 minutes dwell at two major resonances 6.6.3 Operating shock The drive meets the following criteria while operating in the conditions described below.
Page 52: Table 27.Sinusoidal Shock Wave
6.6.4.2 Sinusoidal shock wave The shape is approximately half-sine pulse. The figure below shows the maximum acceleration level and duration. Table 28: Sinusoidal shock wave Models Acceleration level (G) Duration (ms) 1 and 2 disk models 3 disk models All models 6.6.5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis.
Page 53: Table 29.Sound Power Levels
6.8 Identification labels The following labels are affixed to every drive: • A label containing the Hitachi logo, the Hitachi Global Storage Technologies part number and the statement " Made by Hitachi Global Storage Technologies Inc." or Hitachi Global Storage Technol- ogies approved equivalent.
Page 54: Safety
United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon 1211, Halon 1301 and Halon 2402. Although not specified by the Protocol, CFC-112 is also controlled. In addition to the Protocol Hitachi Global Stor- age Technologies requires the following: •...
Page 55: Electromagnetic Compatibility
The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd: Council Directive 89/336/EEC on the approximation of laws of the Member States relating to electromagnetic compatibility.
Page 56 Deskstar 7K250 Hard Disk Drive Specification...
Page 57: Connector Location
7.0 Electrical interface specification 7.1 Connector location Refer to the following illustration to see the location of the connectors Figure 10 : Connector location 7.1.1 DC power connector The DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part number 350078-4 (strip), part number 61173-4 (loose piece), or their equivalents.
Page 58: Table 31.Signal Definitions
7.2 Signal definitions The pin assignments of interface signals are listed as follows: Table 32: Signal definitions SIGNAL Type SIGNAL Type RESET- 3–state DD08 3–state 3–state DD09 3–state 3–state DD10 3–state 3–state DD11 3–state 3–state DD12 3–state 3–state DD13 3–state 3–state DD14 3–state...
Page 59: Table 32.Special Signal Definitions For Ultra Dma
7.3 Signal descriptions Table 33: Special signal definitions for Ultra DMA Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- DD00–DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Regis- ter and ECC access.
Page 60 DASP- This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 kW resistor. During a Power-On initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that device 1 is present.
Page 61 DMACK- This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. This signal is internally pulled up to 5 Volt through a 15kΩ resistor with a resistor tolerance value of –50% to +100%.
Page 62: Interface Logic Signal Levels
7.4 Interface logic signal levels The interface logic signals have the following electrical specifications: Input High Voltage 2.0 V min Inputs Input Low Voltage –0.8 V max. Output High Voltage 2.4 V min. Outputs: Output Low Voltage 0.5 V max. 7.5 Reset timings RESET–...
Page 63: Pio Timings
7.6 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description. CS(1:0)- DA(2:0) DIOR-, DIOW - W rite data DD(15:0) Read data DD(15:0) t7(*) t8(*) IOCS16-(*) IORDY (*) Up to ATA-2 (mode-0,1,2) PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time –...
Page 64: Read Drq Interval Time
7.6.2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows: • In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs •...
Page 65: Multi Word Dma Timings
7.7 Multi word DMA timings The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description. CS0-/CS1- tLR/tLW DMARQ DMACK- tKR/tKW DIOR-/DIOW- READ DATA WRITE DATA PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time – DIOR-/DIOW- asserted pulse width – DIOR- data access –...
Page 66: Ultra Dma Timings
7.8 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, and 4 of the Ultra DMA Protocol. 7.8.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC DSTROBE tZAD DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxx RD Data RD Data...
Page 67: Host Pausing Read Dma
7.8.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (all values in ns) DSTROBE to HDMARDY- – – – – – – – – –...
Page 68: Host Terminating Read Dma
7.8.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxxxxxxxxxxxxxxxxx RD Data xxxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (all values in ns) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tRFS...
Page 69: Device Terminating Read Dma
7.8.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (all values in ns) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Time from DSTROBE edge to –...
Page 70: Initiating Write Dma
7.8.5 Initiating Write DMA DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tACK tCYC tCYC HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (all values in ns) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Unlimited interlock time...
Page 71: Device Pausing Write Dma
7.8.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 DESCRIPTION MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (all values in ns) HSTROBE to DDMARDY- time –...
Page 72: Device Terminating Write Dma
7.8.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 DESCRIPTION MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (all values in ns) tRFS DDMARDY- to final HSTROBE...
Page 73: Host Terminating Write Dma
7.8.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD PARAMETER MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 DESCRIPTION MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (all values in ns) Time from HSTROBE edge to –...
Page 74: Table 33.I/O Address Map
7.9 Addressing of registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0– and CS1–) and three address lines (DA0–2) are used to select one of these registers, while a DIOR–...
Page 75 Part 2. Interface specification Deskstar 7K250 Hard Disk Drive Specification...
Page 76 Deskstar 7K250 Hard Disk Drive Specification...
Page 77: Terminology
8.0 General 8.1 Introduction This specification describes the host interface of the HDS7225xxVLATx0 hard disk drive. The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-6) Revision 3b, dated 26 February 2002, with certain limitations described in Section 8.3 below.
Page 78 Deskstar 7K250 Hard Disk Drive Specification...
Page 79: Table 34.Register Set
9.0 Registers 9.1 Register set Table 35: Register Set Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-) Data bus high impedance Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used...
Page 80: Table 35.Alternate Status Register
9.2 Alternate Status Register Table 36: Alternate Status Register DSC/ SERV This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.
Page 81: Data Register
9.6 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command and the configuration information is transferred on an Identify Device command.
Page 82: Table 37.Drive Address Register
9.8 Drive Address Register Table 38: Drive Address Register -WTG -DS1 -DS0 This register contains the inverted drive select and head select addresses of the currently selected drive. Definitions High Impedance. This bit is not a device and will always be in a high impedance state. -WTG Write Gate.
Page 83: Error Register
9.10 Error Register Table 40: Error Register IDNF ABRT TK0NF AMNF This register contains the status from the last command executed by the device or a diagnostic code. At the comple- tion of any command, except Execute Device Diagnostic, the contents of this register are always valid even if ERR = 0 is in the Status Register.
Page 84: Sector Number Register
9.13 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track. In LBA mode, this register contains Bits 0–7. At the end of the command this register is updated to reflect the cur- rent LBA Bits 0–7.
Page 85 Definitions Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned. DRDY Device Ready.
Page 86 Deskstar 7K250 Hard Disk Drive Specification...
Page 87: Table 41.Reset Response Table
10.0 General operation 10.1 Reset response ATA has the following three types of resets: The device executes a series of electrical circuitry diagnostics, spins up the Power On Reset (POR) head disk assembly, tests speed and other mechanical parametric, and sets default values.
Page 88: Table 42.Default Register Values
10.2 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Table 43: Default Register Values Register Default Value Error Diagnostic Code Sector Count Sector Number Cylinder Low Cylinder High Device/Head...
Page 89: Table 44.Reset Error Register Values
10.3 Diagnostic and Reset considerations For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On Reset DASP– is read by Device 0 to determine if Device 1 is present. If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device 0 clears the BSY bit whenever it is ready to accept commands.
Page 90: Sector Addressing Mode
10.4 Sector Addressing Mode All addressing of data sectors recorded on the device's media is done by a logical sector address. The logical CHS address for HDS7225xxVLATx0 is different from the actual physical CHS location of the data sector on the disk media.
Page 91 The only commands that may be overlapped are NOP (with 01h subcommand code) (’00’h) Read DMA Queued (’C7’h) Service (’A2’h) Write DMA Queued (’CC’h) For the READ DMA QUEUED and WRITE DMA QUEUED commands, the device may or may not perform a bus release.
Page 92: Power Management Features
10.6 Power management features The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.
Page 93: Table 45.Power Conditions
10.6.4 Interface capability for power modes Each power mode affects the physical interface as defined in the following table: Table 46: Power conditions Mode Interface active Media Active Active Idle Active Standby Inactive Sleep Inactive Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.
Page 94: S.m.a.r.t. Function
10.7 S.M.A.R.T. Function The intent of Self-monitoring, analysis, and reporting technology (S.M.A.R.T.) is to protect user data and prevent unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T. devices employ sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition.
Page 95: Error Log
10.7.7 Error log Logging of reported errors is supported. The device provides information on the last five errors that the device reported as described in the SMART error log sector. The device may also provide additional vendor specific information on these reported errors. The error log is not disabled when SMART is disabled. Disabling SMART disables the delivering of error log information via the SMART READ LOG SECTOR command.
Page 96: Security Mode Feature Set
10.8 Security Mode Feature Set Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent unauthorized access to a device even if it is removed from the computer. New commands are supported for this feature as listed below: Security Set Password ('F1'h) Security Unlock...
Page 97: Passwords
10.8.3 Passwords This function can have two types of passwords as described below. Master Password When the Master Password is set, the device does NOT enable the Device Lock Function, and the device CANNOT be locked with the Master Password, but the Master Password can be used for unlocking the locked device.
Page 98 10.8.4.3 Operation from POR after user password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Device Locked mode Unlock CMD Erase Prepare Media Access Non-media Access Command (*1) Command (*1) Erase Unit...
Page 99: User Password Lost
10.8.4.4 User Password lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
Page 100: Table 46.Command Table For Device Lock Operation
10.8.5 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Table 47: Command table for device lock operation Device Mode Device Mode Command Command Locked Unlocked Frozen Locked Unlocked Frozen Check Power Mode...
Page 101: Host Protected Area Feature
10.9 Host Protected Area Feature Host Protected Area Feature provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the main memory of the entire system may also be dumped into the protected area to resume after a system power off.
Page 102: Security Extensions
3. Conventional usage without system software support Since the drive works as a 6.2 GB device, there is no special care required for normal use of this device. 4. Advanced usage using protected area The data in the protected area is accessed by the following steps. i.
Page 103: Seek Overlap
10.10 Seek overlap HDS7225xxVLATx0 provides an accurate method for measuring seek time. The seek command is usually used to measure the device seek time by accumulating the execution time for a number of seek commands. With typical implementation of seek command this measurement must include the device and host command overhead. To eliminate this overhead the drive overlaps the seek command as described below.
Page 104: Write Cache Function
10.11 Write cache function Write cache is a performance enhancement whereby the device reports the completion of the write command (Write Sectors, Write Multiple, and Write DMA) to the host as soon as the device has received all of the data into its buffer. The device assumes the responsibility for subsequently writing the data onto the disk.
Page 105: Reassign Function
10.12 Reassign function The Reassign function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. This reassignment information is registered internally and the information is available right after completing the Reassign function.
Page 106: Power-Up In Standby Feature Set
10.13 Power-Up in Standby feature set The Power-Up In Standby feature set allows devices to be powered-up into the Standby power management state to minimize inrush current at power-up and to allow the host to sequence the spin-up of devices. This feature set will be enabled and disabled via the SET FEATURES command or the use of a jumper.
Page 107: Advanced Power Management Feature Set (Apm)
10.14 Advanced Power Management feature set (APM) This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing advanced power management levels.
Page 108: Automatic Acoustic Management Feature Set (Aam)
10.15 Automatic Acoustic Management feature set (AAM) This feature set allows the host to select an acoustic management level. The acoustic management level may range from the lowest acoustic emanation setting of 01h to the maximum performance level of FEh. Device performance and acoustic emanation may increase with increasing acoustic management levels.
Page 109: Address Offset Feature
10.16 Address Offset Feature Computer systems perform initial code loading (booting) by reading from a predefined address on a drive. To allow an alternate bootable operating system to exist in a system reserved area on a drive, this feature provides a Set Features function to temporarily offset the drive address space.
Page 110: Identify Device Data
10.16.2 Identify Device Data Identify Device data, word 83, bit 7 indicates the device supports the Address Offset Feature. Identify Device data, word 86, bit 7 indicates the device is in Address Offset mode. 10.16.3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error, even if the access protection is removed by a Set Max Address command.
Page 111: Bit Address Feature Set
10.17 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are •...
Page 112 Deskstar 7K250 Hard Disk Drive Specification...
Page 113: Pio Data In Commands
11.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.
Page 114: Pio Data Out Commands
e. The host reads one sector (or block) of data via the Data Register. f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b.
Page 115 • Write Multiple Ext • Write Sector(s) • Write Sector(s) Ext Execution includes the transfer of one or more 512 byte (> 512 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head Registers.
Page 116: Non-Data Commands
11.3 Non-data commands The following are Non-data commands: • Check Power Mode • Device Configuration FREEZE LOCK • Device Configuration RESTORE • Execute Device Diagnostic • Flush Cache • Flush Cache Ext • Idle • Idle Immediate • Initialize Device Parameters •...
Page 117: Dma Commands
11.4 DMA commands The following are DMA commands: • Read DMA • Read DMA Ext • Write DMA • Write DMA Data transfers using DMA commands differ in two ways from PIO transfers: • Data transfers are performed using the Slave DMA channel •...
Page 118: Dma Queued Commands
11.5 DMA queued commands DMA queued commands are • Read DMA Queued • Read DMA Queued Ext • Service • Write DMA Queued • Write DMA Queued Ext 1. Command Issue a. the host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers.
Page 119: Table 47.Command Set (1 Of 2)
12.0 Command descriptions The table below shows the commands that are supported by the device. Table 50: “Command Set (subcommand)” on page 107 shows the subcommands that are supported by each command or feature. Table 48: Command Set (1 of 2) Code Binary Code Bit Protocol...
Page 120: Table 48.Command Set (2 Of 2)
Table 49: Command Set (2 of 2) Binary Code Bit Protocol Command Code (Hex) 7 6 5 4 3 2 1 0 Security Freeze Lock 1 1 1 1 0 1 0 1 Security Set Password 1 1 1 1 0 0 0 1 Security Unlock 1 1 1 1 0 0 1 0 Seek...
Page 121: Table 49.Command Set (Subcommand)
2 : PIO data OUT command 3 : Non data command 4 : DMA command Table 50: Command Set (subcommand) Command Feature Command (Subcommand) Code (Hex) Register (Hex) S.M.A.R.T. Function S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T.
Page 122 The following symbols are used in the command descriptions. Output registers This indicates that the bit must be set to 0. This indicates that the bit must be set to 1. The device number bit. Indicates that the device number bit of the Device/Head Register should be specified. Zero selects the master device and one selects the slave device.
Page 123: Table 50.Check Power Mode Command (E5H/98H)
12.1 Check Power Mode (E5h/98h) Table 51: Check Power Mode command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 124: Table 52.Device Configuration Overlay Features Register Values
12.2 Device Configuration Overlay (B1h) Table 52: Check Power Mode Command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 125: Device Configuration Identify (Subcommand C2H)
12.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.
Page 126: Table 53.Device Configuration Overlay Data Structure
Table 54: Device Configuration Overlay Data structure Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved...
Page 127: Table 54.Dco Error Information Definition
Table 55: DCO error information definition Cylinder high invalid word location Cylinder low invalid bit location (bits 7:0) Sector Number Invalid bit location (bits 15:8) error reason code description DCO feature is frozen Device is now Security Locked mode Device's feature is already modified with DCO User attempt to disable any feature enabled Sector count Device is now SET MAX Locked or Frozen mode...
Page 128: Table 55.Execute Device Diagnostic Command (90H)
12.3 Execute Device Diagnostic (90h) Table 56: Execute Device Diagnostic command (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 129: Table 56.Flush Cache Command (E7H)
12.4 Flush Cache (E7h) Table 57: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 130: Table 57.Flush Cache Ext Command (Eah)
12.5 Flush Cache Ext (EAh) Table 58: Flush Cache Ext Command (EAh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 131: Table 58.Format Track Command (50H)
12.6 Format Track (50h) Table 59: Format Track command (50h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 132: Table 59.Format Unit Command (F7H)
12.7 Format Unit (F7h) Table 60: Format Unit command (F7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 133: Table 60.Identify Device Command (Ech)
12.8 Identify Device (ECh) Table 61: Identify Device command (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 134: Table 61.Identify Device Information (Part 1 Of 7)
Table 62: Identify device information (Part 1 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific. Word Content Description 045AH or drive classi- bit assignments 045Eh fication 15(=0) 1=ATAPI device, 0=ATA device 14 - 8 retired...
Page 135: Table 62.Identify Device Information (Part 2 Of 7)
Table 63: Identify device information (Part 2 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific Word Content Description 0000H Reserved XF00H Capabilities, bit assignments: 15-14(=0) Reserved Standby timer (=1) Values as specified in ATA standard are supported (=0)
Page 136: Table 63.Identify Device Information (Part 3 Of 7)
Table 64: Identify device information (Part 3 of 7) Word Content Description 0003H Flow Control PIO Transfer Modes Supported 15- 8(=0) Reserved 7- 0(=3) Advanced PIO Transfer Modes Supported '11' = PIO Mode 3 and 4 Supported 0078H Minimum Multiword DMA Transfer Cycle Time Per Word 15- 0(=78h) Cycle time in nanoseconds (120 ns, 16.6 MB/s) 0078H Manufacturer's Recommended Multiword DMA Transfer Cycle Time...
Page 137: Table 64.Identify Device Information (Part 4 Of 7)
Table 65: Identify device information (Part 4 of 7) Word Content Description 7BEAH Command set supported 15-14 Word 83 is valid 13(=1) FLUSH CACHE EXT command supported 12(=1) FLUSH CACHE command supported 11(=1) Device Configuration Overlay command supported 10(=1) 48-bit Address Feature Set supported 9(=1) Automatic Acoustic mode 8(=1)
Page 138: Table 65.Identify Device Information
Table 66: Identify device information (Part 5 of 7 Word Content Description XXXXH Command set supported 15-14 Reserved FLUSH CACHE EXT command supported FLUSH CACHE command supported Device Configuration Overlay command supported 48-bit Address Feature Set supported Automatic Acoustic Management enabled SET Max Security extension enabled Set Features Address Offset Feature mode Set Features subcommand required to spin-up after...
Page 139: Table 66.Identify Device Information (Part 6 Of 7)
Table 67: Identify device information (Part 6 of 7) Word Content Description XXXXH Hardware reset result. Bit assignments 15-14 (=01) Word 93 is valid CBLID- status 1=above Vih 0=below Vil 12- 8 Device 1 hardware reset result Device 0 clear these bits to 0 Reserved PDIAG- assertion 1 = asset 0 = not assert...
Page 140: Table 67.Identify Device Information (Part 7 Of 7)
Table 68: Identify device information (Part 7 of 7) An asterisk (*) in next to the Content field indicates the use of those parameters that are vendor specific Word Content Description XXXXH * Current Set Feature Option. Bit assignments 15-4 Reserve Auto reassign 1= enabled...
Page 141: Table 68.Idle Command (E3H/97H)
12.9 Idle (E3h/97h) Table 69: Idle command (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 142: Table 69.Idle Immediate Command (E1H/95H)
12.10 Idle Immediate (E1h/95h) Table 70: Idle Immediate command (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 143: Table 70.Initialize Device Parameters Command (91H)
12.11 Initialize Device Parameters (91h) Table 71: Initialize Device Parameters command (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 144: Table 71.Nop Command (00H)
12.12 NOP (00h) Table 72: NOP Command (00h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 145: Table 72.Read Buffer (E4H)
12.13 Read Buffer (E4h) Table 73: Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 146: Table 73.Read Dma Command (C8H/C9H)
12.14 Read DMA (C8h/C9h) Table 74: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 147 Sector Number This indicates the sector number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 8–15 (Low) and bits16–23 (High).
Page 148: Table 74.Read Dma Ext Command (25H)
12.15 Read DMA Ext (25h) Table 75: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 149 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24)of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8)of the address of the first unrecoverable error.
Page 150: Table 75.Read Dma Command (C8H/C9H)
12.16 Read DMA Queued (C7h) Table 76: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 151 Input parameters from the device on command complete Sector Count Bits 7 - 3 (Tag) contain the Tag of the completed command. Bit 2 (REL) is cleared to zero. Bit 1 (I/O) is set to one. Bit 0 (C/D) is set to one. Sector Number, Cylinder High/Low, H Sector address of unrecoverable error (applicable only when an unrecoverable error has occurred.) Cleared to zero...
Page 152: Table 76.Read Dma Ext Command (25H)
12.17 Read DMA Queued Ext (26h) Table 77: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 153: Sector Count
Input parameters from the device on bus release Sector Count (HOB=0) Bits 7 - 3 (Tag) contain the Tag of the completed command. Bit 2 (REL) is cleared to zero. Bit 1 (I/O) is set to one. Bit 0 (C/D) is set to one. Sector Number, Cylinder High/Low n/a Cleared to zero when the device performs a bus release.
Page 154: Table 77.Read Log Ext Command (2Fh)
12.18 Read Log Ext (2Fh) Table 78: Read Log Ext Command (2Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 155: Table 78.Log Address Definition
Table 79: Log Address Definition Log Address Content Feature set Type Log directory Read Only Extended Comprehensive SMART error log SMART error logging Ready Only SMART self-test log SMART self-test See Note Extended SMART self-test log SMART self-test Read Only 80h-9Fh Host vendor specific SMART...
Page 156: Table 80.Extended Comprehensive Smart Error Log
12.18.2 Extended Comprehensive SMART Error Log The figure below defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty commands such as com- mand codes not implemented by the device or requests with invalid parameters or in valid addresses.
Page 157: Table 82.Command Data Structure
12.18.2.3.2 Data format of command data structure Table 83: Command data structure Description Bytes Offset Device Control register Features register (7:0) (see Note) Features register (15:8) Sector count register(7:0) Sector count register(15:8) Sector number register(7:0) Sector number register(15:8) Cylinder Low register (7:0) Cylinder Low register (15:8) Cylinder High register (7:0) Cylinder High register (15:8)
Page 158: Extended Self-Test Log Sector
Note: bits (7:0) refer to the contents if the register is read with bit 7 of the Device Control register cleared to zero. Bits (15:8) refer to the contents if the register is read with bit 7 of the Device Control register set to one. State shall contain a value indicating the state of the device when the command was issued to the device or the reset occurred as described below.
Page 159 12.18.3.1 Self-test log data structure revision number The value of this revision number shall be 01h. 12.18.3.2 Self-test descriptor index This indicates the most recent self-test descriptor. If there have been no self-tests, this is set to zero. Valid values for the Self-test descriptor index are 0 to 18.
Page 160: Table 84.Read Long (22H/23H)
12.19 Read Long (22h/23h) Table 85: Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 161 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred Sector Number This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7. (L = 1) Cylinder High/Low This indicates the cylinder number of the transferred sector.
Page 162: Table 85.Read Multiple (C4H)
12.20 Read Multiple (C4h) Table 86: Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 163 Cylinder High/Low This indicates the cylinder number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Low), 16–23 (High). (L = 1) This indicates the head number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 24–27.
Page 164: Table 86.Read Dma Ext Command (25H)
12.21 Read Multiple Ext (29h) Table 87: Read DMA Ext Command (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 165 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 166: Table 87.Read Native Max Address (F8H)
12.22 Read Native Max ADDRESS (F8h) Table 88: Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 167: Table 88.Read Native Max Address Ext Command (27H)
12.23 Read Native Max Address Ext (27h) Table 89: Read Native Max Address Ext command (27h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 168: Table 89.Read Sectors Command (20H/21H)
12.24 Read Sectors (20h/21h) Table 90: Read Sectors Command (20h/21h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 169 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 170: Table 90.Read Sector(S) Ext Command (24H)
12.25 Read Sector(s) Ext (24h) Table 91: Read Sector(s) Ext command (24h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 171 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 172: Table 91.Read Verify Sectors (40H/41H)
12.26 Read Verify Sectors (40h/41h) Table 92: Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 173 Cylinder High/Low This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 174: Table 92.Read Verify Sector(S) Command (42H)
12.27 Read Verify Sector(s) (42h) Table 93: Read Verify Sector(s) command (42h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 175 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 176: Table 93.Recalibrate (1Xh)
12.28 Recalibrate (1xh) Table 94: Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 177: Table 94.Security Disable Password (F6H)
12.29 Security Disable Password (F6h) Table 95: Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 178: Table 96.Security Disable Password (F3H)
12.30 Security Disable Password (F3h) Table 97: Security Disable Password (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 179: Table 97.Security Erase Unit (F4H)
12.31 Security Erase Unit (F4h) Table 98: Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 180 If the device receives a Security Erase Unit command without a prior Security Erase Prepare command the device aborts the security erase unit command. This command disables the security mode feature (device lock function), however, the master password is still stored internally within the device and may be reactivated later when a new user password is set.
Page 181: Table 99.Security Freeze Lock Command (F5H)
12.32 Security Freeze Lock (F5h) Table 100: Security Freeze Lock command (F5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 182: Table 100.Security Set Password Command (F1H)
12.33 Security Set Password (F1h) Table 101: Security Set Password command (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 183 Security Level Zero indicates High level. One indicates Maximum level. If the host sets High level and the password is forgotten, the Master Password can be used to unlock the device. If the host sets Maximum level and the user password is for- gotten, only a Security Erase Prepare/Security Unit command can unlock the device and all data will be lost.
Page 184: Table 102.Security Unlock Command (F2H)
12.34 Security Unlock (F2h) Table 103: Security Unlock command (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 185: Table 103.Seek Command (7Xh)
12.35 Seek (7xh) Table 104: Seek command (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 186: Table 104.Service Command (A2H)
12.36 Service (A2h) Table 105: Service command (A2h) Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Feature - - - - - - - - Sector Count - - - - - - - - Sector Number - - - - - - - -...
Page 187: Table 105.Set Features Command (Efh)
12.37 Set Features (EFh) Table 106: Set Features command (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 188: Set Transfer Mode
Note: After the power on reset or hard reset the device is set to the following features as default. Write cache Enable ECC bytes 4 bytes Read look-ahead Enable Reverting to power on defaults Disable Release interrupt Disable 12.37.1 Set Transfer mode When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer mechanism.
Page 189: Automatic Acoustic Management
120 [ y [ 435 [sec] (default: 120 [sec]) = (x − 40h) & 60 +600 (600 [ y [ 4380) [sec] When Low RPM standby mode is the deepest Power Saving Mode and the value in Sector Count register is between 01h and 3Fh, where 120 [ y...
Page 190: Table 106.Set Max Address Command (F9H)
12.38 Set Max ADDRESS (F9h) Table 107: Set Max ADDRESS command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 191 If a host protected area has been established by a Set Max Address Ext command, the device shall return command aborted. Output parameters to the device Option bit for selection whether nonvolatile or volatile. B = 0 is volatile condition. When B=1, MAX LBA/CYL which is set by Set Max LBA/CYL command is preserved by POR.
Page 192: Table 107.Set Max Set Password Command
12.38.1 Set Max Set Password (Feature=01h) Table 108: Set Max Set Password command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 193: Table 109.Set Max Lock Command
12.38.2 Set Max Lock (Feature=02h) Table 110: Set Max Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 194: Table 110.Set Max Unlock Command (F9H)
12.38.3 Set Max Unlock (Feature = 03h) Table 111: Set Max Unlock command (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...
Page 195: Table 111.Set Max Freeze Lock (F9H)
12.38.4 Set Max Freeze Lock (Feature = 04h) Table 112: Set Max Freeze Lock (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data...
Page 196: Table 112.Set Max Address Ext Command (37H)
12.39 Set Max Address Ext (37h) Table 113: Set Max Address Ext command (37h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 197 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by the Set Max Address Ext command is preserved by POR. When B=0, MAX Address which is set by the Set Max Address Ext command will be lost by POR.
Page 198: Table 113.Set Multiple Command (C6H)
12.40 Set Multiple (C9h) Table 114: Set Multiple command (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 199: Table 114.Sleep Command (E6H/99H)
12.41 Sleep (E6h/99h) Table 115: Sleep command (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 200: Table 115.S.m.a.r.t. Function Set Command (B0H)
12.42 S.M.A.R.T. Function Set (B0h) Table 116: S.M.A.R.T. Function Set command (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 201 12.42.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h) This subcommand returns the Attribute Thresholds of the device to the host. Upon receipt of the SMART Read Attribute Thresholds subcommand from the host, the device reads the Attribute Thresholds from the Attribute Threshold sectors and then transfers the 512 bytes of Attribute Thresholds information to the host.
Page 202 host within two seconds after receipt of the new command. After servicing the interrupting command, the device will resume its routine automatically or not start its routine depending on the interrupting command. Captive mode: When executing self-test in captive mode, the device sets BSY to one and executes the specified self-test routine after receipt of the command.
Page 203 Upon receipt of the S.M.A.R.T. Disable Operations subcommand from the host, the device asserts BSY, disables S.M.A.R.T. capabilities and functions, clears BSY, and asserts INTRQ. After receipt of the device of the S.M.A.R.T. Disable Operations subcommand from the host, all other S.M.A.R.T. subcommands—with the exception of S.M.A.R.T.
Page 204: Table 116.Device Attribute Data Structure
12.42.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures are in byte ordering, that is, the least significant byte occupies the lowest numbered byte address location in the field.
Page 205 Attribute ID Numbers: Any nonzero value in the Attribute ID Number indicates an active attribute. The device supports following Attribute ID Numbers. Attribute Name Indicates that this entry in the data structure is not used Raw Read Error Rate Throughput Performance Spin Up Time Start/Stop Count Reallocated Sector Count...
Page 206 12.42.2.3 Off-Line Data Collection Status The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates an Automatic Off-line Data Collection Status. Bit 7 Automatic Off-line Data Collection Status Automatic Off-line Data Collection is disabled. Automatic Off-line Data Collection is enabled.
Page 207: Device Attribute Thresholds Data Structure
Abort/restart off-line by host bit The device will suspend off-line data collection activity after an interrupting command and resume it after a vendor specific event The device will abort off-line data collection activity upon receipt of a new command Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit...
Page 208: Table 118.Device Attribute Thresholds Data Structure
The sequence of active Attribute Thresholds will appear in the same order as their corresponding Attribute Values. Table 119: Device Attribute Thresholds Data Structure Description Byte Offset Value Data Structure Revision Number 0010h 1st Device Attribute 30th Device Attribute 15Eh Reserved 16Ah Vendor specific...
Page 209: Table 120.S.m.a.r.t. Log Directory
12.42.4 S.M.A.R.T. Log Directory The following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log Direc- tory is S.M.A.R.T. Log Address zero and is defined as one sector long. Table 121: S.M.A.R.T. Log Directory Description Byte Offset...
Page 210: Table 122.Error Log Data Structure
12.42.5.4 Error log data structure The data format of each error log data structure is shown below. Table 123: Error log data structure Description Byte Offset 1st command data structure 2nd command data structure 3rd command data structure 4th command data structure 5th command data structure Error data structure 12.42.5.5 Command data structure...
Page 211: Table 125.Self-Test Log Data Structure
The state field contains a value indicating the device state when command was issued to the device. Value State Unknown Sleep Standby Active/Idle S.M.A.R.T. Off-line or Self-test x5h-xAh Reserved xBh-xFh Vendor specific The value of ’x’ is vendor specific 12.42.6 Self-test log data structure The following table defines the 512 bytes that make up the Self-test log sector.
Page 212: Table 126.S.m.a.r.t. Error Codes
12.42.7 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Table 127: S.M.A.R.T. Error Codes Error condition Status Register Error Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the Cylinder High and Cylinder Low registers.
Page 213: Table 127.Standby (E2H/96H)
12.43 Standby (E2h/96h) Table 128: Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 214: Table 128.Standby Immediate (E0H/94H)
12.44 Standby Immediate (E0h/94h) Table 129: Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 215: Table 129.Write Buffer (E8H)
12.45 Write Buffer (E8h) Table 130: Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 216: Table 130.Write Dma (Cah/Cbh)
12.46 Write DMA (CAh/CBh) Table 131: Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 217 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 218: Table 131.Write Dma Ext Command (35H)
12.47 Write DMA Ext (35h) Table 132: Write DMA Ext Command (35h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 219 Cylinder High Current LBA (23:16) Cylinder High Previous LBA (47:40) Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error.
Page 220: Table 132.Write Dma Queued Command Cah/Cbh)
12.48 Write DMA Queued (CAh/CBh) Table 133: Write DMA Queued Command CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 221 Input parameters from the device on command complete Sector Count Bits 7 - 3 (Tag) contain the Tag of the completed command. Bit 2 (REL) is cleared to zero. Bit 1 (I/O) is set to one. Bit 0 (C/D) is set to one. Sector Number, Cylinder High/Low, H Sector address of unrecoverable error (applicable only when an unrecoverable error has occurred).
Page 222: Table 133.Write Dma Queued Ext Command (36H)
12.49 Write DMA Queued Ext (36h) Table 134: Write DMA Queued Ext Command (36h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 223 Input parameters from the device on Bus Release Sector Count Bits 7 - 3 (Tag) contain the Tag of the command being bus released. Bit 2 (REL) is set to one. Bit 1 (I/O) is cleared to zero. Bit 0 (C/D) is cleared to zero. Sector Number, Cylinder High/Low, H n/a.
Page 224: Write Log Ext (3Fh)
12.50 Write Log Ext (3Fh) Table 135: Write Log Ext Command (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 225: Write Long (32H/33H)
12.51 Write Long (32h/33h) Table 136: Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 226 Cylinder High/Low This indicates the cylinder number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 24–27.
Page 227: Write Multiple (C5H)
12.52 Write Multiple (C5h) Table 137: Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 228 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains current the LBA bits 24–27.
Page 229: Write Multiple Ext (39H)
12.53 Write Multiple Ext (39h) Table 138: Write Log Ext Command (3Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 230 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 231: Write Sectors (30H/31H)
12.54 Write Sectors (30h/31h) Table 139: Write Sectors command (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 232 Cylinder High/Low This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Low) and 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 233: Write Sector(S) (34H)
12.55 Write Sector(s) (34h) Table 140: Write Sector(s) Command (34h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 234 Input parameters from the device Sector Number (HOB=0) LBA (7:0) of the address of the first unrecoverable error. Sector Number (HOB=1) LBA (31:24) of the address of the first unrecoverable error. Cylinder Low (HOB=0) LBA (15:8) of the address of the first unrecoverable error. Cylinder Low (HOB=1) LBA (39:32) of the address of the first unrecoverable error.
Page 235: Time-Out Values
13.0 Time-out values The timing of BSY and DRQ in Status Register are shown in the table below. Table 141: Time-out values INTERVAL START STOP TIME-OUT Power On Device Busy After Power On Status Register BSY=1 400 ns Power On Device Ready After Power On Status Register BSY=1...
Page 236 If the host detects a time-out while waiting for a response from the device, we recommend that the host system execute a Soft reset and then retry the command. Deskstar 7K250 Hard Disk Drive Specification...
Page 237 Index 48-bit Address Feature ....................97 Abbreviations ........................1 Acoustics .........................39 Actuator ..........................9 Address Offset ........................95 Advanced Power Managemen ..................93 Automatic Acoustic Management ..................94 BSMI mark ........................41 Cable noise interference ....................32 Cabling ..........................60 Capacity, formatted ......................11 Caution ..........................3 CE mark ..........................41 Command descriptions ....................105 Command overhead ......................15 Command protocol ......................99 Command table .......................86...
Page 238 DMA commands ......................103 DMA Data Transfer commands ..................103 Drive characteristics .......................11 Drive format ........................13 Drive ready time ......................17 Electrical interface ......................43 Electromagnetic compatibility ..................40, 41 Environment ........................28 Fixed-disk subsystem ......................9 Flammability ........................40 Flush Cache ........................115 Formatted capacity ......................11 Functional specification ....................7 General ..........................1 General features ......................5 Head disk assembly ......................9...
Page 239 Labels, Identification ......................39 Latency, average ......................17 Load/unload ........................32 Mechanical specifications ....................33 Mode transition time .......................20 Mounting hole locations ....................34 Mounting orientation ......................35 Non-data commands .......................102 Operating modes ......................20 description 18 Operating shock ......................37 Packaging ........................41 Passwords ........................83 Performance characteristics ....................15 Physical dimensions ......................33 PIO timings ........................49 Power consumption effiency ..................31...
Page 240 S.M.A.R.T. Function Set ....................186 Safety ..........................40 Secondary circuit protection ...................40 Sector Addressing ......................76 Security Mode Feature Set ....................82 Shock ..........................36 Signal definitions ......................44 Specification ........................23 Temperature ........................28 Time-out values ......................221 UL approval ........................40 Vibration .........................36 Weight ..........................33 Write Buffer ........................201...
Page 241 References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information pur- poses only and does not constitute a warranty.

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Hitachi 7K250 - Deskstar - Hard Drive Specifications

Table of Contents

8 General

2 General Features of the Drive

3 Fixed-Disk Subsystem Description

4 Drive Characteristics

4.4.3 Drive Ready Time

5 Defect Flagging Strategy

6 Specification

7 Electrical Interface Specification

10 General Operation

11 Command Protocol

12 Command Descriptions

12.16 Read Dma Queued (C7H)

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Summary of Contents for Hitachi 7K250 - Deskstar - Hard Drive