Sata Ii Optional Features - Hitachi CinemaStar P7K500 Specifications

8.20 SATA II Optional Features

There are several optional features defined in SATA II. The following shows whether these features are
supported or not.
8.20.1 Asynchronous Signal Recovery
The device supports asynchronous signal recovery defined in SATA II.
8.20.2 Device Power Connector Pin 11 Definition
SATA II specification defines that Pin 11 of the power segment of the device connector may be used to
provide the host with an activity indication and disabling of staggered spin-up. The device does not
support both usage of Pin 11.
8.20.3 Phy Event Counters
Phy Event Counters are an optional feature to obtain more information about Phy level events that occur on
the interface. This information may aid designers and integrators in testing and evaluating the quality of the
interface. A device indicates whether it supports the Phy event counters feature in IDENTIFY (PACKET)
DEVICE Word 76, bit 10. The host determines the current values of Phy event counters by issuing the READ
LOG EXT command with a log page of 11h. The counter values shall not be retained across power cycles.
The counter values shall be preserved across COMRESET and software resets.
The counters defined can be grouped into three basic categories: those that count events that occur during
Data FIS transfers, those that count events that occur during non-Data FIS transfers, and events that are
unrelated to FIS transfers. Counters related to events that occur during FIS transfers may count events
related to host-to-device FIS transfers, device-to-host FIS transfers, or bi-directional FIS transfers. A counter
that records bi-directional events is not required to be the sum of the counters that record the same events
that occur on device-to-host FIS transfers and host-to-device FIS transfers.
Implementations that support Phy event counters shall implement all mandatory counters, and
may support any of the optional counters as shown in 0. Note that some counters may increment
differently based on the speed at which non-Data FIS retries are performed by the host and device.
Implementations may record CRC and non-CRC error events differently. For example, there is a
strong likelihood that a disparity error may cause a CRC error. Thus, the disparity error may
cause both the event counter that records non-CRC events and the event counter that records CRC
events to be incremented for the same event. Another example implementation difference is how a
missing EOF event is recorded; a missing EOF primitive may imply a bad CRC even though the
CRC on the FIS may be correct. These examples illustrate that some Phy event counters are
sensitive to the implementation of the counters themselves, and thus these implementation
sensitive counters cannot be used as an absolute measure of interface quality between different
implementations.
8.20.3.1
Counter Reset Mechanisms
There are two mechanisms by which the host can explicitly cause the Phy counters to be reset.
The first mechanism is to issue a BIST Activate FIS to the device. Upon reception of a BIST
Activate FIS the device shall reset all Phy event counters to their reset value. The second
mechanism uses the READ LOG EXT command. When the device receives a READ LOG EXT
command for log page 11h and bit 0 in the Features register is set to one, the device shall return
the current counter values for the command and then reset all Phy event counter values.
8.20.3.2
Counter Identifiers
Each counter begins with a 16-bit identifier. 0 defines the counter value for each identifier. Any unused
counter slots in the log page should have a counter identifier value of 0h.
Optional counters that are not implemented shall not be returned in log page 11h. A value of '0' returned for a
counter means that there have been no instances of that particular event. There is no required ordering for
event counters within the log page; the order is arbitrary and selected by the device vendor.
HITACHI Deskstar & CinemaStar P7K500 Hard Disk Drive specification (Rev 1.1)
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