Table of Contents
Advertisement
3 SPECIFICATIONS
3.4.2 Details of Buffer Memory
3 - 14
Downloaded from
ManualsNet.com
This section describes the details of each item in the buffer memory, shown in Table
3.4 of section 3.4.1.
(1) Input data from slave address 1A to 3A, and some EC flags (Buffer
memory address 0
The input data from the AS-i Ver. 2.11-compatible (Group A) and AS-i Ver. 2.04-
compatible I/O slaves and part of the EC flag of the QJ71AS92 are stored.
Example: Buffer memory address Un\G0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(a) Bit 0: Configuration Error
Bit 0 checks for a configuration error.
A configuration error occurs if the projected slave list (LPS (for read)) and
detected slave list (LDS) are different in the configuration contents.
On detection of a configuration error in the AS-i system, the QJ71AS92
turns ON the corresponding bit of the slave list (addresses: 1D
differs from the buffer memory settings and turns bit 0 ON.
Bit 0 automatically turns OFF when the configuration error is all resolved.
When bit 0 is ON, check whether the wiring is proper and the projected
slave list (LPS (for read)) is the same as the detected slave list (LDS), for
example. (This bit corresponds to the input signal X4.)
(b) Bit 1: AS-i Power Fail (APF)
Bit 1 checks the AS-i power supply status.
The QJ71AS92 turns bit 1 ON when the voltage supplied by the AS-i power
supply is insufficient. It turns OFF automatically when the supplied voltage
is restored.
When bit 1 is ON, check the rated current value of the AS-i power supply,
the wiring, and the overall distance of the system. (This bit corresponds to
the input signal X5.)
search engine
: Un\G0)
H
Bit 0: Configuration Error
0: No configuration error
1: Configuration error occurs
Bit 1: AS-i Power Fail (APF)
0: AS-i Power On (APO)
1: AS-i Power Fail (APF)
Bit 2: Normal Operation Active
0: Normal operation
1: Not normal operation
Bit 3: Configuration Mode Active
0: Not configuration mode
1: Configuration mode
Bit 4 to 7 : Input data from slave address 1A
Bit 8 to 11 : Input data from slave address 2A
Bit 12 to 15 : Input data from slave address 3A
0: OFF
1: ON
MELSEC-Q
to 20
) that
H
H
3 - 14
Advertisement
Table of Contents
