UG-178
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
This section explains the default and optional settings or modes
allowed on the
AD9284
evaluation board.
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and J101.
Analog Input
The A and B channel inputs on the evaluation board are set up as
simultaneous channel sampling using a single transformer (per
channel) analog input with a 50 Ω impedance. The default
analog input configuration supports analog input frequencies
of up to ~200 MHz. This input network is optimized to support
a wide frequency band. See the
information on the recommended networks for different input
frequency ranges. The nominal input drive level is 10.5 dBm to
achieve 1.5 V p-p full scale into 50 Ω. At higher input frequencies,
slightly higher input drive levels are required due to losses in the
front-end network.
VREF
The
AD9284
operates with a fixed 1.0 V reference. This sets the
analog input span to 1.5 V p-p.
AD9284
data sheet for additional
RBIAS
RBIAS has a default setting of 10 kΩ (R206) to ground and is
used to set the ADC core bias current. Note that using a resistor
value other than a 10 kΩ, 1% resistor for RBIAS may degrade
the performance of the device.
Clock Circuitry
The default clock input circuit on the
board uses a simple transformer-coupled circuit using a high
bandwidth 1:1 impedance ratio transformer (T501) that adds a
very low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended sine wave
types of inputs. The transformer converts the single-ended input to
a differential signal that is clipped by CR501 before entering the
ADC clock inputs. The
distribute a single clock to both ADC channels.
Non-SPI Mode
For users who want to operate the DUT without using SPI,
remove the shorting jumpers on J302. This disconnects the
CSB, SCLK, and SDIO/PWDN pins from the SPI control bus,
allowing the DUT to operate in non-SPI mode. In this mode,
the SDIO/PWDN pin takes on an alternate function to enable
power down functionality.
To enable the power-down feature, add a shorting jumper across
J202 at Pin 2 and Pin 3 to connect the SDIO/PDWN pin to
DRVDD.
Rev. A | Page 4 of 24
AD9284-250EBZ User Guide
AD9284
evaluation
AD9284
board has on-chip circuitry to
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