Advanced Chipset Features - CHAINTECH 7AIV2 Manual

User's Manual

3-3 Advanced Chipset Features

By choosing the Advanced Chipset Features option from the CMOS Setup Utility
menu (Figure 3-1), the screen below is displayed. This sample screen contains the
manufacturer's default values for the mainboard.
CMOS Setup Utility- Copyright (C) 1984-2000 Award Software
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
PCI Master Pipeline Req
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4X Mode
AGP Fast Write
Flash BIOS Protection
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
Move Enter:Select
F5:Previous Values
All of the above settings have been determined by the mainboard manufacturer
and should not be changed unless you are absolutely sure of what you are
doing. Explanation of the DRAM timing and chipset features setup is lengthy,
highly technical and beyond the scope of this manual. Below are abbreviated
descriptions of the functions in this setup menu. You can look on the world
wide web for helpful chipset and RAM configuration information including
AWARD's web site at http://www.award.com.
A. BANK 0/1 and 2/3 DRAM Timing
This item allows youto select the value in this field, depending on whether the
board has paged DRAM or EDO (Extended Data Output) DRAMs.
B. SDRAM Cycle Length
When synchronous DRAM is installed, the number of the clock cycles of CAS
latency depends on the DRAM timing. Do not reset this setting from the default
value specified by the system designer.
26
Advanced Chipset Features
SDRAM 8/10ns
SDRAM 8/10ns
3
Host CLK
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
64M
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
+/-/PU/PD:Value
F6:Fail-Safe Defaults
Figure 3-4 Chipset Features Setup Screen
Menu Level
F10:Save ESC:Exit
F7:Optimized Defaults
Item Help
F1:General Help