Advanced Chipset Features - CHAINTECH 6VIA4 User Manual

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Table of Contents

User's Manual

3-3 Advance Chipset Features

By choosing the Advanced Chipset Features option from the Standard CMOS

Features menu (Figure 3-1), the screen below is displayed. This sample screen

contains the manufacturer's default values for the mainboard.

Bank 0/1 DRAM Timing

Bank 2/3 DRAM Timing

SDRAM Cycle Length

DRAM Clock

Memory Hole

P2C/C2P Concurrency

Fast R-W Turn Around

System BIOS Cacheable Disabled

Video RAM Cacheable

AGP Aperture Size

AGP-4X Mode

AGP Comp. Driving

AGP C.Driving Strength

Flash BIOS Protection

Hardware Reset Protect

OnChip Sound

Spectrum Spread

CPU to PCI Write Buffer

PCI Dynamic Bursting

Move Enter:Select

F5:Previous Values

All of the above settings have been determined by the mainboard manufacturer

and should not be changed unless you are absolutely sure of what you are

doing. Explanation of the DRAM timing and chipset features setup is lengthy,

highly technical and beyond the scope of this manual. Below are abbreviated

descriptions of the functions in this setup menu. You can look on the world

wide web for helpful chipset and RAM configuration information including

AWARD's web site at http://www.award.com.

A. BANK 0/1 & 2/3 DRAM Timing

This item allows youto select the value in this field, depending on whether the

board has paged DRAM or EDO (Extended Data Output) DRAMs.

B. SDRAM Cycle Length

When synchronous DRAM is installed, the number of the clock cycles of CAS

latency depends on the DRAM timing. Do not reset this setting from the default

value specified by the system designer.