Table of Contents
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User's Manual
I. CPU to PCI Write Buffer
When Enabled, CPU to the PCI bus are buffered, to compensate for the speed
differences between the CPU and the PCI bus.
J. PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
K. Memory Parity/ECC Check
If the DRAM chips in your system support parity/ECC check, select Enabled
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