Keithley KPCI-PIO96 User Manual page 61

Parallel digital i/o board
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A
Accessories
relay boards 3-7
terminal boards 3-7
Address
base 4-2
base, assignment 2-3, 4-2
data and control registers 2-3, 4-3
definition B-2
AMCC S5933 bus controller 2-3, 4-2, 4-4
AND gate, in debounce circuit 3-9
API
definition B-2
Application program
ISA card port I/O call, using with
KPCI-PIO series 4-4
TestPoint or LabVIEW 2-3, 3-2
Application programming interface
definition B-2
Applications for board, examples 2-2
B
Bad board
checking for 5-3, 5-4
Base address 4-2
assignment 2-3, 4-2
Board
bad, checking for 5-3, 5-4
handling 3-4, 3-6
installing 3-8
returning to Keithley 5-22
spare, using in troubleshooting 5-3, 5-4
unwrapping and inspecting 3-4
Boards, multiple
problems, checking for 5-3, 5-4
Bus
control 2-3
definition B-2
memory assignments 4-2
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Bus controller, AMCC S5933 2-3, 4-2, 4-4
Bus mastering 2-3, 4-2
definition B-2
Byte
definition B-2
C
Cable
for loop-back connections 5-11
for output set test connections 5-17
Cables
locally fabricated 3-6
manufactured 3-7
Common, digital See grounding, signal, I/O
pin assignment
Computer requirements See system requirements
Connection points, locating and identifying 3-5
Connections
accessories 3-6
cables 3-6
external circuits 3-8
external, checking during troubleshooting 5-3, 5-4
pin assignments, I/O connectors 3-5
to external circuits 3-8
using I/O conditioning 3-8
using interface accessories 3-6
using pullups 3-8
Connector
expansion slot, troubleshooting 5-3, 5-4
I/O, mating, type to use 3-5, 5-10, 5-16
loop-back, precautions 5-11
Connectors, I/O
locations 3-6
port group assignments 3-6
Contact Bounce
definition B-2
elimination, circuit 3-9
Contacts
bounce elimination 3-9
monitoring closure 3-8
Index
i-1

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