General Memory Assignments; Control And Data Register Memory Assignments - Keithley KPCI-PIO96 User Manual

4-2 I/O Address Mapping

General memory assignments

Control and data register memory assignments

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NOTE A typical user of the KPCI-PIO96 board does not need to read this
section. Register level programming of your board is neither practical
nor necessary for most users. Register level interfacing with the PCI
bus is more complex than with the ISA bus. PCI board addresses are
mapped automatically in general memory, whereas ISA board ad-
dresses are assigned by the user to memory reserved for I/O.
The DriverLINX driver shipped with your board provides a user-friendly Application
Programming Interface (API) that supports Visual C++, Visual Basic, and Delphi programming
languages under Windows 95/98 and Windows NT 4.0. You are strongly encouraged to use the
capabilities of DriverLINX and ignore the rest of the information in this chapter.
However, there are circumstances in which advanced uses may desire or need to bypass
DriverLINX entirely and write their own drivers. Alternatively, advanced users may wish to use
DriverLINX with programming languages other than Visual C++, Visual Basic, or Delphi.
Ways to accomplish these tasks are referenced under "Setting control and data registers." The
remainder of the chapter summarizes general and relative register addresses and
register assignments.
The PCI specification allows each card to be assigned up to five distinct memory regions. The first
region, BADDR 0, is mandatory per the PCI specification, as published by the PCI Special
Interest Group (PCISIG). BADDR 0 contains all information needed to identify a PCI device.
BADDR 0 also contains specific operation registers for the AMCC S5933 bus controller. These
operation registers hold all control and status information, as well as FIFOs, for PCI-initiated bus
mastering. The other four memory regions are BADDR1, BADDR2, BADDR3, and BADDR4.
These regions are left for custom designs and operate only in the target mode, also called
passthrough operation (memory access through the CPU). High speed data transfer via bus
mastering is unnecessary for the simple digital I/O of the KPCI-PIO96 board.
The KPCI-PIO96 operates in the target mode and uses eight consecutive memory mapped
locations at BADDR1 for its control and data ports. The base address for these locations is
automatically assigned by the Plug and Play feature upon power up. Each offset from the base
address is specified as a multiple of four bytes (module 4 addressing), because each offset
specifies a four byte (32 bit) wide register. Refer to Table 4-1; the prefix '0x' in Table 4-1
designates hexadecimal.
NOTE The term "Base" address in Table 4-1 does not have the same mean-
ing for a PCI board, such as the KPCI-PIO96, as for an ISA board.
The base address for your KPCI-PIO96 is a memory mapped address,
BADDR1, that is assigned by Plug and Play. It is not a fixed, user
assigned I/O address such as 0x300 or 0x310.
KPCI-PIO96 User's Manual