Keithley KPCI-PIO96 User Manual page 30

KPCI-PIO96 User's Manual
Table 4-1
Data and control register addresses
Address
Base + 0x0 offset
*
Base + 0x4 offset
*
Base + 0x8 offset
*
Base + 0xC offset
*
Base + 0x10 offset
Base + 0x14 offset
Base + 0x18 offmset
Base + 0x1C offset
1
Each port group contains a PA port, a PB port and a PC port, as in
the emulated 8255 chip.
* Data Register Format, 32 Bit
4 High
Bits of Port C
MSB
The control register bit assignments for each port group (port group 0 through port group 3) are identical.
These assignments are listed in Table 4-2.
Table 4-2
Control register bit assignments for each port group
Bit
number Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
Port group number: 0, 1, 2 or 3
3
All bit values default to '0' upon computer reset or power-up
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Contents
1
Port group
Port group 1 data
Port group 2 data
Port group 3 data
Control register bits for
port group 0
Control register bits for
port group 1
Control register bits for
port group 2
Control register bits for
port group 3
Not Not
Used Used
Variable name for bit
Not used N/A
Not used N/A
Not used N/A
Not used N/A
I/O direction for PC PCHI[port group
port, upper half
I/O direction for PC PCLO[port group
port, lower half
I/O direction for PB port PB[port group
I/O direction for PA port PA[port group
I/O Function
0 data Read/Write
Read/Write
Read/Write
Read/Write
Write only
Write only
Write only
Write only
4 Low 8 Bits of
Bits of Port C Port B
I/O direction for this port
When bit
value = 0
N/A
N/A
N/A
N/A
2
]_DIR Input
2
]_DIR Input
2
]_DIR Input
2
]_DIR Input
I/O Address Mapping
8 Bits of
Port A
3
When bit
3
value = 1
N/A
N/A
N/A
N/A
Output
Output
Output
Output
4-3
LSB