HP 8924C Assembly page 492

Chapter 11, Block Diagrams
Assembly Details
500-1000 MHz from (A24)
Signal Generator Synth.
J66-3
IN_DET
J67-5,8,9
From Host
Controller
4
J66-12
J66-7
J66-14
Q_NOISE
Q_MOD_OUT
J66-9
J68-7
PWR_DET
XLTR_PWR_DET
J68-17
2
MUX
Power Supplies and Grounds:
Gnd: J68-1,4,6,8,9-16,18-20
J66-1,2,4,5,6,8,10,11,13,15,16,18-20
+12V:_J67-2
12V:_J67-3
+5V:_J67-4
-5V:_J67-7
492
RF Bypass/IQ Modulator Path Switching
Serial
Control
2
Interface
IQ Path Filtering
2
8
Limiter
I_NOISE
I GAIN ADJUST
I_MOD_OUT
I_MOD_DET
Q CHANNEL
SENSE
Q_MOD_DET
I_GAIN
8
Quad
Q_OFFSET
I_OFFSET
DAC
QUAD_ADJ
8
DAC
Q_SENSE
Q_WB_MUX
I_WB_MUX
TB_WB_MUX
CDMA_WB_MUX
MUX_SELECT 0-3
+6V
Green
Reg
LED
-12V
+8V
+9V:_J67-1 Reg
Green
LED
742 MHz LPF
1050 MHz LPF
I_gain_diag
Q_NOT
Q_offset_diag Q_offset_diag
I
I_NOT
Vci_diag
I_offset_diag
Quad_adj_diag
Vblo_diag
Diagnostic MUXs
Vblo_diag
Vci_diag
Vcq_diag
Diagnostic
I_gain_diag
MUX
I_offset_diag
Q_offset_diag
Quad_adj_diag
3
4
4
IN_DET
OUT_DET
Diagnostic
Verr
MUX
I_MOD_DET
Q_MOD_DET
Zero_pwr_RF_det_offset
Di_diag
Dq_diag
1050 MHz LPF
I/Q_OUT
J66-17
To Output
Assembly
OUT_DET
I/Q Modulator
0°
90°
Q
Vcq_diag
Verr
Quadrature Adjust
N:\mkt\MANUALS\HP8924C\ALR\blkdia.fb
(A26)
Di_diag
Dq_diag
J68-3
IQ_WB_MUX
J67-6
IQ_DIAG