HP 8924C Assembly page 476

J65
RESET 1
A13
C2,11-14 GADDR
A1-8
GDATA
G W/R
A10
10,11,12,13
14,15,16,17 D_L_DataStruct
A11
G_INTerupt
A12
18
Diagnostic LEDs
J64
C6
20ms clock
B31 PP2S (2 second clock)
Power Supplies and Ground:
Ground
(J64) A9,11,15,17,19 - B20,23 - C9
(J65) B2,12,22,31
(J64) A32, B32, C32
+5V
(J65) B1, 13,32 - C32
68EC020
Microprocessor
(25 Hz)
First In First
Out (FIFO)
Interface
to the Host
Data and
Controller
Address Buses
Address
Decode
Boot
ROM
FLASH
Memory
Flash Mem.
Controller
SRAM
+15V
(J65) B3
+12.3V
(J64)C31
(J64)A31
+12.3V
CDMA Data
CODEC HDBO-7
(Encoder/
HRW
Decoder)
HSCC (CS1)
Interface
HSINT (CS1)
HCCE. (CS2)
HCCINT (CS2)
CODEC_ADR_0
CODEC_ADR_1
CODEC_ADR_2
Dual
PROTO_DIAG_OUT
Universal
Asynchronous
PROTO_DIAG_IN
Receiver/
Transmitter
PROTO_SER_OUT
(DUART)
PROTO_SER_IN
Multi-
PROTO_TRIG1
Function
Peripheral
PROTO_TRIG2
SYS_RESET (CS1)
SPC_RST (CS2)
A6 PROTOCOL PROCESSOR
(A6-BD.FB)
J64
A13,14
Data To/From
B13,14,15
the Cell Site
C13,14,15
Digital
C18
Assemblies
B17
B19
C17
C19
A16
B16
C16
J65
To rear-panel
B4
Diagnostic/
Protocol
B5
Connector
B6
B7
J64
A7
To rear-panel
Cellsite/Triggers
Connector
B7
C12 To Cell Site
Digital
Assemblies
C10