Cgfsysenb] (Clock Supply And Stop Register B For Fsys) - Toshiba TXZ+ Series Reference Manual

1.4.2.11. [CGFSYSENB] (Clock supply and stop register B for fsys)

Bit Bit Symbol
31 IPENB31
30 IPENB30
29 IPENB29
28 IPENB28
27 IPENB27
26 IPENB26
25 IPENB25
24 IPENB24
23 IPENB23
22 IPENB22
21 IPENB21
20 IPENB20
19 IPENB19
18 IPENB18
17 IPENB17
16 IPENB16
15 IPENB15
14 IPENB14
13 IPENB13
12 IPENB12
11 IPENB11
10 IPENB10
9 IPENB09
After
Type
reset
Clock enabling of SIWDT
1 R/W 0: Clock stop
1: Clock supply
1 R/W Write as "1"
1 R/W Write as "1"
1 R/W Write as "1"
Enable the Clock of PORT W
0 R/W 0: Clock stop
1: Clock supply
0 R Read as "0".
Enable the Clock of UART ch7
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of UART ch6
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of TRGSEL channel0, channel1
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of TRM
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of OFD
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of CRC
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of RAM PARITY
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of DAC channel1
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of DAC channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of COMP channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of ADC Unit A
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of I2C channel3
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of I2C channel2
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of I2C channel1
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of I2C channel0
0 R/W 0: Clock stop
1: Clock supply
Enable the Clock of UART channel5
0 R/W 0: Clock stop
1: Clock supply
0 R/W Enable the Clock of UART channel4
44 / 72
TMPM3H Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2022-05-10
Rev. 1.3