Cgfcen] (Clock Supply And Stop Register For Fc); Cgspclken] (Clock Supply And Stop Register For Adc And Debug Circuit); Rlmlosccr] (Low Speed Oscillation Control Register); Rlmshtdnop] (Power Supply Cut Off Control Register) - Toshiba TXZ+ Series Reference Manual

1.4.2.12. [CGFCEN] (Clock supply and stop register for fc)

Bit Bit Symbol
31:8 -
7 FCIPEN07
6:0 -

1.4.2.13. [CGSPCLKEN] (Clock supply and stop register for ADC and Debug circuit)

Bit Bit Symbol
31:17 -
16 ADCKEN
15:1 -
0 TRCKEN

1.4.2.14. [RLMLOSCCR] (Low speed oscillation control register)

Bit Bit Symbol
7:2 -
1 -
0 XTEN
Note1: It is initialized only by a Power On Reset.
Note2: It is a register accessed per byte. Bit band access is not allowed.

1.4.2.15. [RLMSHTDNOP] (Power supply cut off control register)

Bit Bit Symbol
7 RTLDOLVL
6:1 -
0 PTKEEP
Note: Register access is only the byte unit. Bit band access is not allowed.
After
Type
reset
0 R Read as "0"
Enable the clock for DNF unit A, unit B and unit C.
0 R/W
0: Clock stop
1: Clock supply
0 R Read as "0"
After
Type
reset
0 R Read as "0"
Enable the clock for ADC.
0 R/W 0: Clock stop
1: Clock supply
0 R Read as "0"
Clock Enable of the Debug circuit (Trace/SWV).
0 R/W 0: Clock stop
1: Clock supply
After
Type
reset
0 R Read as "0"
0 R/W Write as "0"
Selection of an external low speed oscillator of operation
0 R/W 0: Stop
1: Oscillation
After
Type
reset
0 R/W Write as "0"
0 R Read as "0".
The I/O control signal in the STOP2 mode is held.
0: Control by Port
1: Hold the state when it changes into "1" from "0".
0 R/W
It is necessary to set this bit prior to the transition to STOP2
mode.
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TMPM3H Group(1)
Clock Control and Operation Mode
Function
Function
Function
Function
TXZ+ Family
2022-05-10
Rev. 1.3