Response Delay Time - Mitsubishi Electric MELSECQ Series User Manual

5
FUNCTIONS
5.6
5
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Response Delay Time

This section described the response delay time of I/O signals and buffer memory.
Maximum delay time [ms] = [Time of (1)] + [Maximum time of (2)]
(1) Scan time of a sequence program
The CPU module processes I/O signals by refreshing them all at once before the
operation start of a sequence program. Therefore, the signals are delayed.
Use direct access input (DX) or direct access output (DY) to minimize the delay.
For details on direct access input (DX) or direct access output (DY), refer to the
following:
• QnUCPU User's Manual (Function Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program
Fundamentals)
(2) Control cycle (1ms) of the QD63P6
The QD63P6 reads out the output signals and buffer memory data updated by the
sequence program and completes processing with up to 2ms (1 control cycle
delay.
The update timing of the input signals and buffer memory data vary within the range of
a control cycle.
5.6 Response Delay Time
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= Scan time of a sequence program + 2 [ms]
2)
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