ST STM32F0 Series Application Note page 14

Power supplies of the STM32F06xxx family
Low-power management reset
A low-power management reset can be generated by entering Stop mode. This type of reset
is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop
mode entry sequence is successfully executed, the device is reset instead of entering Stop
mode.
Option byte loader reset
The option byte loader reset is generated when OBL_LAUNCH (bit 13) is set in the
FLASH_CR register. This bit launches the option byte loading by software.
Power reset
A power reset sets all registers to their reset values, except the backup domain. It is
generated while the NPOR pin is low. For more information concerning NPOR, you must
refer to Section 2.2.1: External power-on reset and power-down reset
Backup domain reset
A backup domain reset only affects the backup domain. It is generated when one of the
following events occurs.
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. VDD power-up if VBAT has been disconnected when it was low.
3. RTC tamper detection event.
4. Change of the read out protection from level 1 to level 0.
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(NPOR).