ST STM32F0 Series Application Note page 9

AN4080
Low-power management reset
There are two ways to generate a low-power management reset:
1. Entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in
User Option Bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
2. Entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User
Option Bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
Option byte loader reset
The option byte loader reset is generated when OBL_LAUNCH (bit 13) is set in the
FLASH_CR register. This bit launches the option byte loading by software.
Power reset
A power reset sets all registers to their reset values, except the Backup domain. It is
generated when one of the following events occurs.
1. Power-on/power-down reset (POR/PDR reset).
2. Exiting Standby mode.
Backup domain reset
A backup domain reset only affects the backup domain. It is generated when one of the
following events occurs.
1. Software reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. VDD power up if VBAT has been disconnected when it was low.
3. RTC tamper detection event.
4. Change of the read out protection from level 1 to level 0.
Power supplies of the STM32F05xxx family
Doc ID 023035 Rev 2 9/29