Table of Contents
Advertisement
8-1-7 Option Bit
The MN101C117 and the MN101CP117 control the oscillation mode after resetting
as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address
(X'7FFF) of the built-in ROM.
Option bit
7
6
5
PKGSEL2 PKGSEL1
Fig. 8-1-2 Option bit(Address: X'07FFF')
4
3
2
1
WDSEL2 WDSEL1
0
NSSTRT
NSSTRT
0
1
WDSEL2 WDSEL1
0
0
1
1
X
PKGSEL2 PKGSEL1
0
X
0
1
1
Chapter 8 Appendices
Selection of oscillation mode
after resetting
Slow mode
NORMAL mode
Watchdog timer cycle setting
16
fs/2
18
fs/2
20
fs/2
Package
SDIP042-P-0600
QFP044-P-1010
QFH048-P-0707
EPROM Versions
137
Advertisement
Table of Contents
