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6-2 A/D Conversion
The procedures for operating the A/D conversion circuit are listed below.
(1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one
of pins AN7 to AN0 (PA7 to PA0) as the analog input.
(2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D
conversion clock. Make this setting such that the period of the conversion clock
(T
), which is based on the oscillator, is greater than 800ns.
AD
(3) With the ANSH1 and ANSH0 flags of A/D control register 0, set the sample-and-hold
time. Select a value for the sample and hold time that is suitable for the analog input
impedance.
(4) Set the ANLADE flag of A/D control register 0 to "1" so that current flows through
the ladder resistors and the A/D converter is on standby.
Note: Steps 1 to 4 above may performed all at the same time.
(5) Set the ANST flag of A/D control register 1 (ANCTR1) to "1" to start the A/D
conversion.
(6) After the sample-and-hold time set in step 3, the sampled A/D conversion data is
sequentially compared to determine its value beginning with the MSB.
(7) When the A/D conversion is complete, the ANST bit is cleared to "0" and conversion
results are stored in A/D buffers (ANBUF0, 1). At the same time, an A/D complete
interrupt request (ADIRQ) is generated.
T
AD
ANST
A/D conversion start
Sampling
A/D interrupt
Figure 6-2-1 A/D Conversion Timing
1~2
3
4
T
S
Hold
Bit 9
Bit 8
comparison
comparison
Determine
Determine
bit 9 value
bit 8 value
12
A/D conversion complete
Bit 0
comparison
Determine
Determine
bit 1 value
bit 0 value
Chapter 6 A/D Conversion Functions
Start the A/D conversion after the
current flowing through the ladder
resistors stabilizes. The time
constant calculated time from the
ladder resistance (max. 80 k Ω )
and the external bypass capacitor
connected between V
and V
dd
should be used as the criteria for
the wait time.
A/D Conversion
ss
115
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