Panasonic MN101C00 User Manual page 49

Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR)
The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR,
ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial
interrupts, A/D conversion complete interrupts, and interrupt request/enable.
Be sure to disable all interrupts before writing to these registors.
7 6
TMnICR, TBICR, SCnICR,
xxxLV1 xxxLV0
ATCICR, ADICR
Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR,
SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)
5 4 3 2 1
– – – – xxxIE
0
(at reset: 00----00)
xxxIR
xxxIR Interrupt request flag
0 No interrupt request
1 Happens interrupt request
xxxIE Interrupt enable flag
0 Disable interrupt
1 Enable interrupt
xxxLV1 xxxLV0 Interrupt level flag
This 2-bit flag sets the interrupt level by
assigning an interrupt level of 0 to 3 to
interrupt requests.
Chapter 2 Basic CPU Functions
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
Interrupts
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